Method for determining on-chip sheet resistivity

Details Method for determining on-chip sheet resistivity Method for determining on-chip sheet resistivity

1999-08-12

2002-06-11

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C438S017000, C324S719000, C257S048000

Reexamination Certificate

active

06403389

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit manufacturing. In particular, the present invention relates to determining values of sheet resistivity for use in an integrated circuit design to ensure manufacturability and performance.
2. Discussion of the Related Art
Interconnect process parameters are parameters that represent the physical properties of interconnect layers (i.e., conductors used in connecting circuit elements of an integrated circuit) and the intervening insulator layers. Interconnect process parameters include physical dimensions and coefficients of conducting and insulating properties. Typical interconnect process parameters used in designing integrated circuits include thicknesses, widths, and such material properties as sheet resistances of conducting layers (e.g., polysilicon and metal) and permittivities of intervening insulator layers (e.g., silicon dioxides). From measurements of these interconnect process parameters, the electrical properties of conductive traces of an integrated circuit can be individually modeled as resistances, capacitances, and inductances. The resistances, capacitances and inductances can be obtained numerically for any structure manufactured under a manufacturing process using simulation programs, including programs commonly referred to as “field solvers”.
A field solver is a computer program which calculates a distribution of an electric field, based on solving the Poisson's equation numerically in two or three dimensions. Thus, a field solver can be used to calculate interconnect electrical properties (e.g., resistances and capacitances) based on a physical model of an interconnect structure. One such field solver, named “Raphael™”, is available from Avant! Corporation, Fremont, Calif. Alternatively, the “QuickCap™” program available from Random Logic Corporation, Fairfax, Va., while strictly speaking not a field solver, can also be used.
In the prior art, field solvers did not play a direct role in determining values of interconnect process parameters. Instead, values of interconnect process parameters are derived from measurements using test structures designed to allow the values of the interconnect process parameters to be computed using closed-form formulae. Typically, a field solver is used only to check whether the values of these interconnect process parameters obtained from these close-formed formulae correctly predict the electrical properties of structures.
Because the interconnect structures in an integrated circuit design below the half-micron level typically contribute a substantial portion of the signal propagation delays, variations in these interconnect structures can result in significant variations in the electrical properties of the interconnect, and thus significant variations in circuit performance. Thus, interconnect process parameters must be accurately extracted. Alternatively, the physical dimensions of interconnect structures are obtained primarily by measuring, for example, scanning-electron microscope (SEM) micrographs of one or more cross-sections of a fabricated test structure. However, poor instrument calibrations can limit the accuracy of such measurements.
In the prior art, when interconnect structures account for a much smaller portion of the electrical properties of the integrated circuit, interconnect process parameters are measured by process engineers for process monitoring purposes, rather than for obtaining accurate measurements of the electrical properties under various load conditions. Consequently, AC and DC electrical measurements are performed on relatively simple test structures (e.g., the van der Pauw structure can be used to measure conductor and diffusion sheet resistances. Similarly, a parallel-plate capacitor can be used to measure capacitance per unit area). Typically, however, these measurements are used to determine directly the capacitance associated with a particular structure, not to determine values of the underlying interconnect process parameters. For example, a parallel-plate structure can be used to determine the capacitance per unit area of a conductor plate. As another example, a conductor line can be provided over a conductor plate. The capacitance per unit length of the conductor line can be determined from such a structure. However, such simple test structures are unsuitable for modeling local variation effects of electrically conductive traces.
Examples of a resistance measurement and a sheet resistivity measurement are provided here.
FIG. 6
shows schematically a four-point Kelvin technique in the prior art for measuring the resistance value of a device
6000
(e.g., a resistor) in an integrated circuit. In
FIG. 6
, device
6000
is connected to four terminals (pads)
6001
-
6004
. According to the four-point Kelvin technique, a current I is forced through device
6000
via terminals
6001
and
6002
, resulting in a voltage difference V1−V2 across device
6000
. The voltage difference is measured across the other two terminals
6003
and
6004
. The resistance R of device
6000
is provided by:
R=(V1−V2)/I.
Sheet resistance p is a convenient measure of resistivity of a conducting layer. In the prior art, to measure resistivity, one form of the four-point Kelvin structure, known as a van der Pauw structure can be used. A van der Pauw structure
800
is shown in FIG.
8
. As shown in
FIG. 8
, test structure
800
includes probe pads
801
-
804
, and a cross-shaped structure
805
, which is formed by conductor traces
805
a
,
805
b
,
805
c
and
805
d
in the conductor layer for which sheet resistance is to be determined. Conductor traces
805
a
-
805
d
intersect at a square portion
805
e
. The resistance of square portion
805
e
is used to determine the sheet resistance of interest. As in the resistance measurement discussed above, a current I is forced across probe pads
804
and
803
in test structure
800
, and a voltage difference &Dgr;V=V2−V1 is measured across probe pads
801
and
802
. In test structure
800
. the sheet resistance &rgr; is given by the relation:
&rgr;=&pgr;/ln(2)*&Dgr;V/I
However, van der Pauw structures are difficult to use in highly conductive layers, such as aluminum. In highly conductive layers, resistivity &rgr; is small. Consequently, the sheet resistance of a square of conductor having this resistivity is also low. As a result, a high current I through the test structure is required to create a measurable voltage difference &Dgr;V. Such a large current can cause a heating effect that affects measurement accuracy and, in some instances, can destroy the test structure.
“Micro-loading” is an effect caused by the local density of conductors within the same conductive layer on each other. Micro-loading, which can result in non-uniformity in conductor widths, occurs in an area of low local conductor density where the etchant is locally depleted due to removal of a large amount of material. Micro-loading results in an under-etching of the conductive layer, i.e., the resulting conductor widths are wider than desired. Conversely, in an area of high local conductor density, an excessive amount of active etchant can remain when only a small amount of conductive material is to be removed. The excess amount of active etchant results in an over-etching of the conductive layer, i.e., resulting conductor widths are narrower than desired.
The non-uniformity resulting from micro-loading, or other mechanisms leading to an under-etch or an over-etch of a conductor, can be characterized by an interconnect process parameter “CD loss.” CD loss affects the electrical characteristics (e.g., a resistance or a capacitance) of a conductor. Thus, CD loss is an important design parameter. Test structures such as test structure
800
, or similar structures with a square or nearly-square central region, are often used because of relative insensitivity to CD loss. In test structure
800
, for example, the square central region
805
e
maintain

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