Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1999-10-19
2002-02-19
Christianson, Keith (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
Reexamination Certificate
active
06348701
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to test structures and methods used in semiconductor device fabrication.
2. Description of the Related Art
Damascene refers to a process for making interconnect lines in a semiconductor device. In a damascene structure
100
shown in
FIG. 1A
, damascene trenches
101
and
105
are formed using conventional patterning (e.g. lithography and etching) techniques. A diffusion barrier
102
is deposited on the trenches to prevent leakage of subsequently deposited metal
103
into a dielectric layer
104
. In this particular example, metal
103
is copper while dielectric layer
104
is a low dielectric constant (“low-k”) dielectric material such as TEOS.
Chemical mechanical planarization (“CMP”) is used to remove portions of metal
103
which are outside the trenches and to obtain a flat surface for subsequent formation of overlying layers. CMP removes material from the semiconductor wafer by pressing the device side of the wafer against a rotating polishing pad in the presence of a slurry.
FIG. 1B
depicts structure
100
after a CMP process. A post-CMP clean is performed on the wafer containing structure
100
immediately after the CMP process to remove contaminants, residual slurry, and loose metal particles that were introduced during polishing.
As shown in
FIG. 1B
, a poor post-CMP clean can leave metal atoms
107
in field area
108
,thereby causing a line-to-line short between trenches
101
and
105
. Line-to-line shorts can lead to device unreliability if not catastrophic failure. Thus, the amount of metal atoms left in the area between the trenches (the field area) must be periodically determined and analyzed to ensure that metal atoms are adequately removed by the post-CMP clean process. Common methods for measuring metal concentrations in field areas include Secondary Ion Mass Spectroscopy (“SIMS”), Auger mapping, and Electron Energy Loss Spectroscopy (“EELS”). These methods, however, require expensive equipment and long setup time.
Thus, it is highly desirable to have a fast, sensitive, and simple technique for measuring metal concentrations in a field area.
SUMMARY OF THE INVENTION
In an embodiment of the invention, a voltage is applied on a first trench structure while a second trench structure is grounded. The resultant current is measured and used as an indicator of metal concentration in the field area between the trench structures.
REFERENCES:
patent: 5751015 (1998-05-01), Corbett et al.
Joo Young-Chang
Marathe Amit P.
Christianson Keith
Kwok, Esq. Edward C.
LandOfFree
Method for determining metal concentration in a field area does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for determining metal concentration in a field area, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for determining metal concentration in a field area will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2953726