Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-19
2002-06-18
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06408426
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to integrated circuit interconnect routing, and more particularly to a method for determining locations of interconnect repeater farms during the physical design stage of integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits comprise a plurality of electronic components that function together to implement a higher-level function. ICs are formed by implanting a pattern of transistors into a silicon wafer which are then connected to each other by layering multiple layers of metal materials, interleaved between dielectric material, over the transistors. The fabrication process entails the development of a schematic diagram that defines the circuits to be implemented. A chip layout is generated from the schematic. The chip layout, also referred to as the artwork, comprises a set of planar geometric shapes over several layers that implement the circuitry defined by the schematic. A mask is then generated for each layer based on the chip layout. Each metal is then successively manufactured over the silicon wafer according to the layer's associated mask using a photolithographical technique.
The process of converting the specifications of an electrical circuit schematic into the layout is called the physical design process. CAD tools are extensively used during all stages of the physical design process. The physical design process is accomplished in several stages including partitioning, floorplanning, and routing.
During the partitioning stage, the overall integrated circuit is partitioned into a set of functional subcircuits called blocks. The block partitioning process considers many factors including the number and size of the blocks, and number of interconnections between the blocks. The output of partitioning is a set of blocks along with a set of interconnections required between blocks, referred to herein as a netlist.
During the floorplanning stage, a floorplan is developed defining the placement and rectangular shape of each block. The goal of the floorplanning stage is to select the optimal layout for each block, as well as for the entire chip.
Once an acceptable floorplan is developed, the interconnections between the blocks (as defined by the netlist) are routed. The space not occupied by the blocks is partitioned into rectangular regions referred to as channels. Interconnects are preferably routed within the designated channels, but may also be routed through defined feedthroughs through the blocks, or in defined over-the-block routing space.
The goal of a router is to complete all circuit connections resulting in minimal interconnect signal delay. Where possible, the router will generally attempt to route individual interconnects on a single layer; however, if this is not achievable given the topology of the netlist, an interconnect may be routed over two or even more layers. Often, interconnect routes resulting from the autorouting will be too long to meet signal delay specifications. The delay results from the inherent RC characteristics of the interconnect line. Signal transition time can often be significantly improved by introducing one or more signal repeaters along the path of the interconnect line.
Over the past decades, integrated circuits (ICs) of increasingly higher density have been developed to meet industry demands of higher performance and smaller packaging. The very high densities of today's integrated circuits means that more metal layers and interconnects per layer are required than ever before. The result is that the routing task has become even more complex, often resulting in a higher number of interconnects that do not meet the timing criteria, and therefore an increasingly higher number of required repeaters.
When over-the-block routing is employed, the insertion of repeaters along the over-the-block interconnects is problematic due to the need to be able to connect from the metal layer on which the problem interconnect resides, through any intervening layers, to the repeaters ports. More particularly, in order to be able to insert a repeater at a location along the interconnect, necessary metal resources must be reserved in order to create the connections between the interconnect and repeater ports through any intervening metal layers.
Because the locations of the optimal repeater locations is unknown prior to routing the interconnects, repeater locations are typically constrained to lie in reserved repeater areas called “repeater farms”. This allows the necessary metal resources to be reserved in each layer prior to routing to guarantee the ability to complete interconnect-to-repeater connections of repeaters inserted along interconnects within a repeater farms.
The process of determining the best locations of the repeater farms has itself become complex. The increased number of interconnects required by higher density circuits increases the likelihood of more problem interconnects generated during the routing phase. The limitation of repeater locations to repeater farms along with the higher number of interconnects increases the possibility that no satisfactory route solutions exist for an interconnect. Thus, unless the repeater farms are optimally located, the probability of an increased number of unsatisfactory interconnects is higher in higher density circuits. Accordingly, a need exists for a method for determining optimal locations of interconnect repeaters farms during the physical design of an integrated circuit. It would be desirable if this method were automated.
SUMMARY OF THE INVENTION
The present invention is a novel method and system for optimally locating interconnect repeater farms during the physical design of an integrated circuit. In accordance with the invention, the optimal unconstrained repeater locations is calculated in an unconstrained mode to generate a list of unconstrained legal repeater locations for a given routing list. A set of repeater farms are defined to encompass areas of concentration of the calculated unconstrained legal repeater locations. The optimal constrained repeater locations are than calculated, constraining the repeater locations to locations within the repeater farms. A set of sub-optimal nets are then selected to include those nets of the routing list that were hurt the most as a result of the constraint to the repeater farms. The optimal unconstrained repeater locations of the selected sub-optimal nets are then calculated and additional repeater farms are defined to encompass areas of concentration of the optimal unconstrained repeater locations of the sub-optimal nets. The process repeated until desired performance gain is achieved.
REFERENCES:
patent: 5799170 (1998-08-01), Drumm et al.
patent: 5859999 (1999-01-01), Morris et al.
patent: 5860017 (1999-01-01), Sharangpani et al.
patent: 5912820 (1999-06-01), Kerzman et al.
patent: 5923570 (1999-07-01), Shigemoto
patent: 5946477 (1999-08-01), Ito
patent: 6266803 (2001-07-01), Scherer et al.
Brasen et al. (“Post-placement buffer reoptimization”, Proceedings of Compass Design Automation, Euro ASIC '92, Jun. 1, 1992, pp. 156-161).*
Tellez et al. (“Minimal buffer insertion in clock trees with skew and slew rate constraints”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 4, Apr. 1997, pp. 333-342).*
Zhou et al. (“Simultaneous routing and buffer insertion with restrictions on buffer locations”, Proceedings of 36th Design Automation Conference, Jun. 21, 1999, pp. 96-99).*
NN9305307 (“Clock Distribution Tree for Minimal Clock Skew”, IBM Technical Disclosure Bulletin, vol. 36, No. 5, May 1993, pp. 307-308 (4 pages)).*
Wolfe, Alexander, “Patents Shed Light on Merced,” Electronic Engineering Times, Feb. 15, 1999, pp. 43-44.
Interactive Repeater Insertion Simulator (IRIS) System And Method, application NO. 09/329556, Filed Jun. 10, 1999, Inventor: John D. Wanek.
Josephson Jon Eric
Wanek John D
LandOfFree
Method for determining locations of interconnect repeater... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for determining locations of interconnect repeater..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for determining locations of interconnect repeater... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2948074