Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-04-12
2005-04-12
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S001000, C257S202000
Reexamination Certificate
active
06880145
ABSTRACT:
A method for interconnecting a plurality of dies. The method generally includes receiving a plurality of interconnect requirements for the dies. The interconnect requirements may include a priority for each of a plurality of nets. A position and an angle for one of the dies relative to a substrate may be calculated in response to the interconnect requirements. A plurality of nets may then be routed among the dies and a plurality of substrate pads defining external connections for the substrate. The dies may be mounted to the substrate after routing has been finalized.
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Lie James H.
Wright Andrew J.
Cypress Semiconductor Corp.
Maiorana PC Christopher P.
Thompson A. M.
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