Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1999-06-04
2001-07-24
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C324S1540PB
Reexamination Certificate
active
06265233
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to a method for determining a crack limit of a film deposited on a semiconductor wafer, and more particularly to a method for determining a crack limit of an undoped silicon glass (USG) film deposited on a wafer by a chemical vapor deposition (CVD) process.
BACKGROUND OF THE INVENTION
An undoped silicon glass (USG) film deposited by a chemical vapor deposition (CVD) process has been widely used in the field of IC fabrication as a shallow trench isolation (STI) gap fill, sidewall spacer, inter-metal dielectric (IMD) or passivation dielectric. For the CVD process, O
3
/TEOS is preferred over SiH
4
due to better gap fill or step coverage capability as well as safety consideration. On the other hand, a sub atmosphere (SA) CVD process is prior to an atmosphere (AP) CVD process and a plasma enhanced (PE) CVD process to serve as the deposition technique for depositing the USG film because of the better balance in the deposition rate and the gap fill capability. Therefore, so far, an SA O
3
/TEOS process is commonly used for the deposition of a USG film.
The SA O
3
/TEOS process, however, still suffers from a drawback that the as-deposited film is porous and inclined to absorb moisture. Therefore, a post annealing procedure will be necessary to densify the film. In the meantime, the within film tensile stress is subject to elevation during the thermal annealing procedure so as to cause the film crack. Therefore, the situation of the USG film during the IC production is generally checked to detect or even prevent the crack of the film, and it is preferred to adopt a non-destructive method.
Several parameters of the within film such as the deposition rate and the HF etching rate have been monitored to determine the crack limit of the film in order to prevent from cracking, but none of them is sensitive enough to serve as an indicator to achieve this purpose. In addition, a painstaking scanning electron microscope (SEM) process can be used to check the situation of the USG film via an off line operation, and the SEM results generally tell the crack situation of the film rather than prevent it.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method for determining a crack limit of a film deposited on a semiconductor wafer without any destruction.
Another object of the present invention is to provide a method sensitive and effective to determine a crack limit of a film deposited on a semiconductor wafer.
A further object of the present invention is to provide a method for determining a crack limit of a film deposited on a semiconductor wafer, which is performed prior to the IC production so that no more off line inspection is required.
According to the present invention, a method for determining a crack limit of a target film deposited on a wafer in production after a post annealing procedure includes steps of:
a) forming a plurality of target films on respective bare wafers;
b) annealing the bare wafers with the target films;
c) detecting thermal shrinkage rates of the annealed target films; and
d) determining the crack limit according to the thermal shrinkage rates of the annealed target films.
Preferably, the plurality of target films are formed on the respective bare wafers with at least two kinds of thickness in order to make the test results on the bare wafers as complete as possible.
For obtaining comparable results, the conditions for forming and annealing the target films on the bare wafers are preferably identical to those for forming and annealing the target film on the wafer in production.
In the step c), each of the thermal shrinkage rates (SR) of the annealed target films is defined by an equation of SR=(T1−T2)/T1, in which T1 indicates the thickness of a target film detected before the annealing procedure, and T2 indicates the thickness of a target film detected after the annealing procedure.
After the thermal shrinkage rates are determined in the step c), the crack limit can be determined for example by selecting the highest one of the thermal shrinkage rates of the annealed target films which do not crack as a threshold value, and subtracting a buffer value from the threshold value to have the crack limit. The presence of the buffer value is for further assuring of the perfection of the target film on the wafer in production when the test results on bare wafers are applied to the production wafers. As for the selection of the buffer value, it can be made by a trial and error method, or as large as possible provided that other desired properties are not influenced significantly.
REFERENCES:
patent: 4249988 (1981-02-01), Lavigna
patent: 5212111 (1993-05-01), Doan
patent: 5554390 (1996-09-01), Anne
patent: 5719495 (1998-02-01), Moslehi
patent: 5795378 (1998-08-01), Sakamoto
patent: 5854302 (1998-12-01), Foster
patent: 6091131 (2000-07-01), Cook
patent: 6174814 (2001-01-01), Cook
Chu Jason C. S.
Hung Roger Tun-Fu
Lin Jerry C. S.
Wu Chih-Ta
Conlin David G.
Corless Peter F.
Dike, Bronstein, Roberts & Cushman Intellectual Property Group
Mosel Vitelic Inc.
Niebling John F.
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