Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2008-01-29
2008-01-29
Dinh, Son (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S154000, C365S156000, C714S720000
Reexamination Certificate
active
07324391
ABSTRACT:
A method (200) for determining various bit failure modes in a static random access memory device. A hard/soft bit failure test sequence is performed on each cell of the memory device to determine whether the cell exhibits a hard bit failure or a soft bit failure, then a data retention test is performed on the cell having soft bit failure to determine whether the cell exhibits a data retention failure. A write or disturb test sequence is then performed on the cell not having data retention failure, and a read or disturb test sequence is performed on the cell having write or disturb failure. Finally, a disturb test sequence is performed on the cell having read or disturb failure, and then an analysis is performed on the data from the tests to determine whether the cell exhibits one of a write, read, or disturb failure.
REFERENCES:
patent: 4879690 (1989-11-01), Anami et al.
patent: 6992916 (2006-01-01), Liaw
patent: 2004/0015757 (2004-01-01), Ohlhoff et al.
Khan Md Abul Bashar
Lescrenier Jon Charles
Loh Wah Kit
San Kemal Tamer
Brady III W. James
Dinh Son
Garner Jacqueline J.
Nguyen N
Telecky , Jr. Frederick J.
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