Method for detecting under-etched vias

Details Method for detecting under-etched vias Method for detecting under-etched vias

1997-12-23

1999-05-11

Rosenberger, Richard A.

Optics: measuring and testing

Inspection of flaws or impurities

Bore inspection

3562371, 356445, G01N21/84

Patent

active

059033436

ABSTRACT:
Methods for detecting under-etched vias, spaces, or under-polished portions in a wafer stack are disclosed. The wafer stack comprises a dielectric layer disposed on a metal layer. The dielectric layer has a plurality of vias etched therein. The wafer stack, including the plurality of vias, is exposed to an etchant which is configured to etch the metal layer at a substantially faster rate than the dielectric layer. As a result, cavities are formed in the metal layer below properly-etched vias. Then, the vias in the wafer stack are optically inspected to detect and identify under-etched vias, which reflect more light than the cavities etched into the metal layer.

REFERENCES:
patent: 5214283 (1993-05-01), Le
patent: 5301012 (1994-04-01), King et al.

Affiliated with

Also associated with

Rating

Method for detecting under-etched vias does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for detecting under-etched vias, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for detecting under-etched vias will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-249307