Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-05-19
2010-12-14
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C382S149000, C430S030000
Reexamination Certificate
active
07853920
ABSTRACT:
One embodiment of a method for detecting, sampling, analyzing, and correcting hot spots in an integrated circuit design allows the identification of the weakest patterns within each design layer, the accurate determination of the impact of process drifts upon the patterning performance of the real mask in a real scanner, and the optimum process correction, process monitoring, and RET improvements to optimize integrated circuit device performance and yield. The combination of high speed simulation coupled with massive data collection capability on actual aerial images and/or resist images at the specific patterns of interest provides a complete methodology for optimum RET implementation and process monitoring.
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Gassner Michael J.
Juang Shauh-Teh
Preil Moshe E.
Wiley James N.
Ye Jun
ASML Netherlands B.V.
Pillsbury Winthrop Shaw & Pittman LLP
Sandoval Patrick
Siek Vuthe
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