Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-01-30
2002-05-14
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000
Reexamination Certificate
active
06388913
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for detecting polarization of a ferroelectric capacitor in a ferroelectric memory and thereof structure, which detecting polarization of a ferroelectric capacitor through a characteristic which present different voltage values by providing different voltages on the ferroelectric capacitor stay at different polarization directions, so that the disadvantages caused by a conventional method for detecting charge quantity can be improved.
BACKGROUND OF THE INVENTION
Currently, electric memories can be split up into two types based on their functions, the one is random access memory (RAM) and the other is non-volatile read only memory (ROM). The differences between two types are the write speed and the function of memory. Because the electric memories cannot equip the above two functions simultaneity, so that the application of the electric memories have been limited. Therefore, many scientists and scholars make an effort to find a solvent. Thereupon, a ferroelectric film has a higher dielectric and a ferroelectric characteristic has been submitted to solve the above problems.
Referring to
FIG. 1
, it is a schematic view of a structure of a conventional non-volatile ferroelectric memory cell. As shown in
FIG. 1
, a conventional non-volatile ferroelectric memory cell
10
comprises an NMOS transistor
12
and a ferroelectric capacitor
14
. The structure of
FIG. 1
is similar to a DRAM
1
T-
1
C structure, the difference is the dielectric layer of the capacitor in a DRAM cell is replaced by a ferroelectric material, so that the data can be written and measured through different polarization directions of the ferroelectric material.
FIGS.
2
A~
2
D show schematic views of an operation principle of a conventional ferroelectric memory cell has
1
T-
1
C structure.
When a voltage VDD is provided to the ferroelectric capacitor
14
, the ferroelectric film of the ferroelectric capacitor
14
would be polarized and a polarization value Pr would be remained. Since the polarization value +Pr is decided as a logic “0”, the −Pr is determined as a logic “1”, as shown in FIG.
2
A. When reading a data, a positive voltage pulse VDD can be provided to a memory cell, as shown in FIG.
2
B. The decision includes two manners. The one is, detecting during a voltage pulse is imposed, so that the voltage values “1” and “0” on the bit line (BL) in proportion to polarization values, as shown in FIG.
2
C. The other is, if the logic state of a cell is “0”, the polarization of the ferroelectric film will be changed from Ps to Pr after a voltage pulse is imposed and a small current generated can be observed. On the other hand, if the logic state of a cell is “1”, the polarization of the ferroelectric film will be changed from Ps to −Pr and a great current generated can be observed. Thus, the logic state of the cell can be derived via in comparison of the difference between the small current and the great current, as shown in FIG.
2
D. In above two manners, a storage state of a primary data would be destructed because the issue of a voltage pulse must be provided to the ferroelectric capacitor
14
, thus the above action is referred as a destructive read out (DRO). To refresh the storage state of the primary data of a memory cell, it is necessary for rewriting after reading.
That is, the conventional technology has been limited. For example, when the polarization of the ferroelectric capacitor is changed and the charge quantity is detected by using the DRO method, however, the charge quantity is related and limited to the size of the ferroelectric capacitor. But, in a writing case, the size of the ferroelectric capacitor cannot be too great.
SUMMARY OF THE INVENTION
The present invention provides a method for detecting polarization of a ferroelectric capacitor in a ferroelectric memory and thereof structure, which detecting polarization of a ferroelectric capacitor through a characteristic which present different voltage values by providing different voltages on the ferroelectric capacitor stay at different polarization directions, so that the disadvantages caused by a conventional method for detecting charge quantity can be improved, and a size limitation of the cell ferroelectric capacitor can be solved.
The present invention provides a method for detecting polarization of a ferroelectric capacitor in a ferroelectric memory, wherein the ferroelectric memory comprises a memory array, the memory array at least comprises a cell ferroelectric capacitor, the cell ferroelectric capacitor is connected in serial to a sense linear capacitor outside the memory array through a bit line and is received a read voltage V
R
, the method comprising the steps of: at first, detecting an output voltage on a connection node between the cell ferroelectric capacitor and the sense linear capacitor. Then, if the detected output voltage is high read voltage, a logic state of the cell ferroelectric capacitor is decided to a first logic state. And, if the detected output voltage is low read voltage, a logic state of the cell ferroelectric capacitor is decided to a second logic state.
The present invention provides a structure of detecting polarization of a ferroelectric capacitor in a ferroelectric memory, the structure at least comprises a memory array and a sense linear capacitor. The memory array at least comprises a depletion mode NMOS transistor and a cell ferroelectric capacitor. The depletion mode NMOS transistor has a source terminal connected to a bit line and a gate terminal connected to a word line. The cell ferroelectric capacitor is connected in serial between a drain terminal of the depletion mode NMOS transistor and the word line. The sense linear capacitor is disposed outside the memory array and is connected in serial between an output terminal of the bit line and a sense voltage.
REFERENCES:
patent: 5432731 (1995-07-01), Kirsch et al.
patent: 5487030 (1996-01-01), Drab et al.
patent: 5729488 (1998-03-01), Drab et al.
patent: 6172897 (2001-01-01), Shuto
patent: 6195281 (2001-02-01), Kim
Chen Shue-Shuen
Kuo Tung-Cheng
Lung Hsiang-Lan
Hoang Huan
Macronix International Co. Ltd.
Powell Goldstein Frazer & Murphy LLP
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