Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
1999-05-14
2001-01-16
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S229000
Reexamination Certificate
active
06175530
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to programmable devices such as field programmable gate arrays, and specifically to methods for alerting users of a low power condition.
BACKGROUND OF THE INVENTION
FIG. 1
shows a conventional Field Programmable Gate Array (FPGA)
1
having an array of configurable logic blocks (CLBs)
2
surrounded by input/output blocks (IOBs)
3
. The CLBs
2
are individually programmable and can be configured to perform a variety of logic functions ranging from simple AND gates to more complex functions of a few input signals. A programmable interconnect structure
4
includes a matrix of programmable switches (PSMs)
5
which can be programmed to selectively route signals between the various CLBs
2
and IOBs
3
and thus produce more complex functions of many input signals. The IOBs
3
can be configured to drive output signals from the CLBs
2
to external pins (not shown) of FPGA
1
and/or to receive input signals from the external FPGA pins.
The CLBs
2
, IOBs
3
, and PSMs
5
of FPGA
1
are programmed by loading configuration data into memory cells (not shown for simplicity) connected to CLBs
2
, IOBs
3
, and PSMs
5
. These memory cells control various switches and multiplexers within respective CLBs
2
, IOBs
3
, and PSMs
5
which implement logic and routing functions specified by the configuration data in the memory cells. Configuration data is provided to FPGA
1
via a configuration port
6
and thereafter routed to the memory cells using a dedicated configuration structure (not shown here but described in U.S. Pat. No. Re 34,363, U.S. Pat. No. 5,430,687, 5,742,531, and 5,844,829). Configuration port
6
is connected to the dedicated configuration structure by a configuration access port (CAP)
7
, which is essentially a bus access point. Further information regarding various types of FPGAs can be found in “The Programmable Logic Data Book 1998” , published in 1998 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
Configuration data is typically downloaded to an FPGA from a host system such as a personal computer or workstation using an FPGA interface cable, as illustrated in FIG.
2
. Well known design tool software operating on a suitable microprocessor within host system
20
creates a configuration bitstream which embodies the logic functions desired to be implemented by the target FPGA. The configuration bitstream is downloaded from host system
20
to interface cable
15
using, for instance, a serial port or a USB port. The interface cable
15
preferably includes an on-board FPGA that customizes the configuration bitstream received from the host system
20
into a format usable by target FPGA
10
, although in some embodiments host system
20
's microprocessor is used to customize the configuration bitstream for target FPGA
10
. Since an FPGA is able to customize configuration data at a rate much faster than that of a microprocessor, FPGA interface cables having an on-board FPGA provide superior performance.
The interface cable receives its power from an external source such as, for instance, from within a board holding the target FPGA. If power to the interface device falls below a minimum operating voltage, components on the interface device such as, for instance, the on-board FPGA and microcontroller may fail. Since the user is typically not alerted to such low power conditions, the sudden non-responsiveness of the microcontroller resulting from insufficient voltage supply may mistakenly be interpreted as the microcontroller “freezing.” It would be desirable to alert the user to such low power conditions so that the user may take suitable action such as, for instance, aborting a download process.
SUMMARY OF THE INVENTION
The present invention provides a method of alerting a user to a low power condition on, for instance, an FPGA interface device. In accordance with the present invention, an interface device having a microcontroller and an associated power plane for powering the microcontroller and other components on the interface device includes a detection circuit coupled to monitor the voltage level of the associated power plane. When the voltage level of the voltage plane falls below a predetermined threshold voltage, the detection circuit sends a low power flag to a host system. The low power flag, which is preferably sent to the host system using a USB port connection, alerts the host system to the low power condition on the interface device. The predetermined threshold voltage is selected to be a suitable amount higher than the minimum operating voltage for the microcontroller so as to allow sufficient time for the microcontroller to send the low power flag to the host system. In response thereto, the host system may take suitable action such as, for instance, alerting the user, resetting the microcontroller, aborting a download process, and so on.
REFERENCES:
patent: Re. 34363 (1993-08-01), Freeman
patent: 5430687 (1995-07-01), Hung et al.
patent: 5844829 (1998-12-01), Freidin et al.
patent: 5901103 (1999-05-01), Harris, II et al.
“The Programmable Logic Data Book”, 1998, available from Xilinx Inc., 2100 Logic Drive, San Jose, California, 95124.
Resler Edwin W.
St. Pierre, Jr. Donald H.
Theron Conrad A.
Fears Terrell W.
Paradice William L.
Xilinx , Inc.
Young Edel M.
LandOfFree
Method for detecting low power on an FPGA interface device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for detecting low power on an FPGA interface device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for detecting low power on an FPGA interface device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2536692