Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
1998-09-22
2003-10-28
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C386S349000, C327S018000
Reexamination Certificate
active
06640328
ABSTRACT:
TECHNICAL FIELD
This invention relates to electronic systems, and more particularly to a method and system for detecting dropouts in data delivered over a bandwidth-limited bus from a source of digital data to a computer system.
BACKGROUND
“Video capture” involves a process of extracting digitized audio/video information from a video image stream comprising a sequence of electronically-encoded image frames with accompanying sound. The audio/video source be a signal conforming to one of the well-known NTSC, PAL, or SECAM standards, or a video camera, or recorded audio/video signals played on a video cassette recorder (VCR) or the like. The target output system may be, for example, a personal computer system.
For example,
FIG. 1
is a block diagram of a prior art electronic video decoder system
1
and computer system
2
. Any of several video sources, such as a video camera
3
, VCR
4
, or a television antenna or cable signal source
5
processed through an RF tuner Sa, are coupled to the video decoder system
1
, which may be, for example, a Rockwell Semiconductor Systems Bt848A single-chip video capture processor and PCI Bus Master, available from Rockwell Semiconductor Systems, Newport Beach, Calif. The video decoder system
1
can place video data directly into the system memory
6
of the computer system
2
. The computer system
2
includes the system memory
6
, a central processing unit
7
, and a host bridge
8
to couple the computer system to a conventional high-speed bus
9
, such as the PCI Bus. The video decoder system
1
can also provide video data to a computer graphics adapter
10
, which includes a graphics controller
11
, a frame buffer
12
, and a RAMDAC
13
. The output of the video decoder system
1
is placed into a target area in the frame buffer
12
for video overlay applications, so that a video image stream may be displayed on a monitor
14
.
The video decoder system
1
includes a video decoder module
20
for converting the input video signal to a decoded digital format. The video decoder module
20
may include an analog-to-digital converter (ADC) and other video processing circuitry, as known in the art. This digital video information is temporarily stored in a first-in-first-out (FIFO) memory
22
. A PCI Bus Master circuit
23
provides controlled transfer of digitized data from the FIFO memory
22
over the bus
9
to the system memory
6
of the computer system
2
.
Audio data from certain signal sources is processed by a separate audio decoder circuit
27
, which generates an analog signal to an audio subsystem
28
of the computer system
2
for playback through a speaker system
29
.
The inventors have determined that it would be useful to use the processing capabilities of the computer system
2
to decode an audio signal within a video decoder system, thus obviating the need for a separate audio decoder circuit and analog cabling to the audio subsystem. This capability would require that an input audio signal be digitized by an ADC, stored in a portion of the FIFO memory
22
(or a separate FIFO memory), and be transferred over the bus
9
to the system memory
6
of the computer system
2
in a steady stream. However, a problem with bus-mastering decoders is that the bandwidth of the bus
9
, particularly the well-known PCI bus, is limited. Under congested conditions, this bandwidth limitation can lead to a certain number of dropouts when delivering data at high-speed from a FIFO memory to the system memory
6
. Dropouts are caused when the FIFO memory overruns due to insufficiently frequent PCI bus accesses. More particularly, during a data transfer from the FIFO memory over the bus
9
to the system memory
6
, a write pointer within the video decoder system
1
begins incrementing, providing an address for the system memory
6
into which to write the data. Incrementation of the write pointer is ostensibly in lock-step with the writing of the data into the system memory
6
via a fast direct memory access (DMA) operation. However, if a dropout occurs due to lack of a bus access, the data is never written into the system memory
6
. Such dropouts are not too objectionable in video-in-a-window applications (where the eye tends to integrate out instantaneous blips), but they can cause major audible clicks and pops when audio data is being transmitted. Design of a solution is complicated by the fact that there can be no guarantee that any data placed in a FIFO memory will actually be delivered to system memory
6
.
The inventors have determined that there is a need for a method for detecting dropouts in digital data delivered over a bandwidth-limited bus from a source of digital data to a computer system. The present invention provides a method and system for achieving this end.
SUMMARY
The invention provides a method and system for detecting dropouts in digital data transferred over a bandwidth-limited bus from a source of digital data to a computer system. Within the digital data source, audio data is sampled and monitored to replace every instance of a selected code value with a nearby code value in order to preserve one code value as an “illegal” code. The data is then placed in an internal buffer memory. During an initialization procedure within the computer system, before any transfer from the digital data source buffer memory to the system memory, the contents of all memory addresses into which audio data is to be written are first preset to the selected “illegal” code value. Thereafter, the digital data source attempts to write data from its buffer memory over the bus into the audio data buffer. Normally, a sequential set of addresses in the audio data buffer will be accessed for writing audio data values. If a dropout does not occur, all of the preset data values will be overwritten with valid data. However, if a dropout over the bus occurs, the digital data source continues to increment its write pointer, thus increasing the address count. After the cause of the dropout terminates, data again flows from the buffer memory over the bus into the audio data buffer. However, because the write pointer has incremented its address count, the next location to which audio data is written is not contiguous to the last written location. In between the next location and the last written location are one or more memory locations that have a value equal to the selected “illegal” code value. Thus, a dropout has the effect of failing to overwrite whatever data happened to be in the buffer before writing recommences. Such illegal code values may be detected after the digital data source is done filling the audio data buffer in the system memory.
REFERENCES:
patent: 4680647 (1987-07-01), Moriyama
patent: 4860121 (1989-08-01), Gotoh
patent: 4937686 (1990-06-01), Arai et al.
patent: 5627846 (1997-05-01), Carr
patent: 5677752 (1997-10-01), Miyamori et al.
patent: 6002724 (1999-12-01), Kaku et al.
patent: 6044338 (2000-03-01), Akune
patent: 6151634 (2000-11-01), Glaser et al.
Brooks John M.
DiMeo Matthew J.
Mair Steven S.
Marotta Daniel A.
Abraham Esaw
Conexant Systems Inc.
Procopio Cory Hargreaves & Savitch LLP
Tu Christine T.
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