Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-10-20
2001-07-10
Teska, Kevin J. (Department: 2763)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06260185
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method and an automatic designing device for designing semiconductor integrated circuits, and more particularly to a designing method and an automatic designing device suitable for designing such semiconductor integrated circuits as general-purpose processors, signal processors, video processors, etc. including logic circuits in part.
1. Background Art
In the IEEE TRANSACTIONS ON COMPUTERS, Vol. c-35, No.8, August 1986, pp. 677-691 (hereinafter referred to as Cited Reference 1), an effective method for logic operations using binary decision diagrams is disclosed.
Also, Proceedings of 1994 Autumn Convention of the Institute of Electronics, Information and Communication Engineers of Japan, edition of fundamentals and interfaces, p. 64 (hereinafter referred to as Cited Reference 2), shows a configuration method of a pass transistor circuit which uses a logic expression called as a binary decision diagram.
2. Disclosure of the Invention
In recent LSI circuit designing practice, automatic designing methods using gate arrays, standard cells, FPGA (field programmable gate arrays), PLA (programmable logic arrays), etc. are in widespread use.
As the number of elements which can be integrated in an LSI has increased significantly, it has become practically impossible for engineers to design manually such large scale and complex logic circuits.
FIG.
13
(
a
) shows a concrete example of standard cell scheme for automatic designing of a logic LSI. In this example, circuits (
1304
,
1305
,
1306
) having certain functions and already layouted, called as cells (
1301
,
1302
,
1303
) are prepared. The LSI has logic circuit areas (
1307
,
1309
,
1311
) and interconnected as required over routing areas (
1308
,
1310
), and wirings are formed over cells, if necessary, to attain a desired logic.
As for so-called “macro” circuits having high regularity such as arithmetic circuits and memories, small-scale blocks are designed manually and these blocks are arranged regularly. In most designing practice of a LSI chip, the macro circuits thus designed are often combined with portions designed by the standard cell scheme or other automatic designing scheme except for a case of designing a specific LSI chip dedicated for an arithmetic unit or a memory. An example of this kind of LSI is shown in FIG.
13
(
b
).
It is desirable that LSI circuits have reduced circuit area, higher speed in operation and lower consumption in power. Therefore, any of various circuit schemes satisfying these requirements as much as possible is to be selected. In selection of a circuit scheme on the premise of automatic designing, however, only such requirements as good circuit performance, small circuit area and lower power consumption are insufficient. That is, automatic designing techniques including logic synthesis technique, automatic layout technique, etc. for supporting a selected circuit scheme must be established.
At present, automatic designing techniques field-proven for CMOS circuits using N-channel and P-channel field effect transistors in complementary arrangement and have been adopted prevalently in development of microprocessors, etc.
On the other hand, a pass transistor circuit scheme is known as an advantageous approach for forming circuits having high speed, small area and low power consumption. As to automatic designing technology for using the pass transistor circuit scheme, a logic circuit configuration method such as disclosed in Cited Reference 2 is available. In the pass transistor circuit scheme, a given logic function is transformed into a logical expression using a binary decision diagram, nodes in the diagram are further transformed into selectors comprised of pass transistors, and then buffers are inserted to produce a logic circuit (called as a pass transistor logic circuit).
FIG. 12
shows a pass transistor logic circuit configuration procedure and an example of a logic circuit configured thereby. Since a circuit configuration procedure has been clearly shown, even a highly complex logic circuit is undoubtedly realizable with pass transistors. This signifies that the pass transistor circuit scheme is advantageously applicable to automatic designing of LSIs.
As mentioned above, in designing large scale and complex logic LSIs, there is a close relationship between circuit schemes and automatic designing techniques, and both can be put into practice only after both are available. In consideration of this condition, the pass transistor circuit configuration method disclosed in Cited Reference 2 is advantageous with respect to an aspect of circuit area, power consumption and performance and an aspect of automatic designing.
However, the present inventor's analysis of a pass transistor logic circuit configured by the method shown in Cited Reference 2, has revealed that since the configured pass transistor logic circuit inherits features of binary decision diagrams, only a source input is applicable as an input from another pass transistor circuit to each pass transistor circuit included in the pass transistor logic circuit.
That is, as a gate input to each pass transistor in the configured pass transistor logic circuit, an input signal of a relevant logic function (or its inverted signal) is applied directly in any case. In this respect, the present inventors have found that there are two problems mentioned below.
The first problem is as follows: In the worst case of this circuit scheme, a signal must go through a number of stages of pass transistors which stages are proportional to the number of input signals on which the output logic depends, causing an increase in delay time.
The second problem is as follows: Since intrinsically shareable logic are arranged individually, the number of circuit elements is increased.
Therefore, the present inventors have proposed to add a signal supplying scheme in which an output signal from another pass transistor circuit is also used as a gate input of a transistor in a pass transistor circuit, in addition to an input signal of a relevant logic function (or its inverted signal). This makes it possible to provide improvements in the number of elements, delay time, circuit area and power consumption, thereby enabling implementation of more complex circuit logic. Examples of circuits arranged in the above-mentioned scheme are shown in FIGS.
4
(
a
) and (
b
) and
5
(
a
) and (
b
).
FIGS.
4
(
a
) and (
b
) show the first problem that delay time increases. In both the circuits shown in FIGS.
4
(
a
) and
4
(
b
), the same logic function is implemented (OUT=A·B·D·E·G·H+A·B·DN·F+A·B·EN·F+AN·C+BN·C, where ‘AN’, etc. represents a negation signal of ‘A’). The circuit shown in FIG.
4
(
a
) has been formed using the conventional designing method presented in Cited Reference 2. In this circuit, delay time of output
401
is defined as a period of time to be taken from the moment a signal is applied to input
402
until it reaches the output through path
403
. As indicated in this Figure, the signal must go though five stages of pass transistor
404
to
408
.
The circuit shown in FIG.
4
(
b
) has been formed using the semiconductor integrated circuit designing method in accordance with the present invention. In this circuit, delay time of output
409
is defined as a period of time to be taken from the moment a signal is applied to input
410
until it reaches the output through path
411
. As indicated in this Figure, the signal has only to go through just three stages of pass transistors
412
to
414
. In general, a delay time increases with an increase in the number of pass transistor stages which a signal goes through. It is therefore understood that reduction in delay time is not sufficient in the circuit shown in FIG.
4
(
a
), which has been formed using the conventional designing method.
FIGS.
5
(
a
)and (
b
) show the second problem that since intrinsically shareable logic components are arranged individually, the number of elements increases, thereby to increase occupie
Sasaki Yasuhiko
Seki Koichi
Yamashita Shunzo
Yano Kazuo
Hitachi , Ltd.
Jones Hugh
Mattingly Stanger & Malur, P.C.
Teska Kevin J.
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