Method for designing semiconductor integrated circuit

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Optimization

Reexamination Certificate

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Details

C716S110000, C716S113000, C716S118000, C716S119000, C716S132000, C716S134000, C703S019000

Reexamination Certificate

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08060850

ABSTRACT:
A method for designing a semiconductor integrated circuit, includes: disposing a plurality of cells in a cell layout region on the basis of a net list indicating connection relations of the plurality of cells to satisfy a setup timing condition; generating a plurality of power regions dividing the cell layout region into plurality; calculating a consumption current of each of the power regions by using a cell power file indicating a consumption current of each of the cells; adjusting layout positions of the temporarily disposed cells with reference to the consumption current of each of the power regions in a range that the setup timing condition is not violated; and optimizing hold timing of the cells after the position adjustment of the cells.

REFERENCES:
patent: 6523154 (2003-02-01), Cohn et al.
patent: 6938233 (2005-08-01), Satoh et al.
patent: 7480875 (2009-01-01), Satoh et al.
patent: 7836415 (2010-11-01), Ushiyama
patent: 2003-330986 (2003-11-01), None

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