Method for designing semiconductor integrated circuit,...

Details Method for designing semiconductor integrated circuit,... Method for designing semiconductor integrated circuit,...

2005-02-28

2008-10-28

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C713S400000, C713S500000

Reexamination Certificate

active

07444606

ABSTRACT:
In lower hierarchy design in which a plurality of circuit blocks are independently designed, a reset adjustment circuit propagating deactivation transition of a reset signal to flip-flops in synchronization with a clock signal is inserted immediately after a reset input pin in each circuit block, and timing adjustment using the clock signal as a reference is implemented for signal paths of the reset signal from the reset adjustment circuit to the flip-flops. In upper hierarchy design in which an entire semiconductor integrated circuit is designed, timing adjustment using the clock signal as a reference is implemented for signal paths of the reset signal, according to setup times and hold times of the reset signal that are prescribed respectively for the reset input pins of the circuit blocks.

REFERENCES:
patent: 6189133 (2001-02-01), Durham et al.
patent: 2003/0061584 (2003-03-01), Shih et al.
patent: 07-168652 (1995-07-01), None
patent: 08-076893 (1996-03-01), None
patent: 11-088306 (1999-03-01), None

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