Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-11-10
2002-01-01
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06336205
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a method for designing a semiconductor integrated circuit. More particularly, the present invention relates to a method for designing a semiconductor integrated circuit with the number of redundant registers cut down during a layout phase to effectively minimize chip area and power needed.
Examples of conventional techniques of cutting down the number of redundant registers in a synchronous circuit includes a method for optimizing the layout of a sequential circuit as disclosed in Japanese Laid-Open Publication No. 8-314998.
According to this publication, layout optimization is allegedly accomplished by performing the process steps of:
1) inputting a sequential circuit to be optimized (e.g., a flip-flop);
2) drawing up a transition implication graph with attached register information about the sequential circuit input;
3) extracting a partial circuit from the transition implication graph, representing the partial circuit as a partial graph and then modifying the partial graph in such a manner as to reduce the respective numbers of edges and registers;
4) generating a partial circuit corresponding to the partial graph modified; and
5) adding the resultant partial circuit to the sequential circuit, thereby eliminating the redundancy.
The conventional method for optimizing a sequential circuit, however, is applicable only to a logical design phase, at which the delay of the circuit is not taken into consideration. Thus, this method is not applicable to various design phases beginning with the layout phase, in which delay is one of essential parameters of the physical design. Also, since this optimization is carried out at the logical design phase, the logic once defined will possibly change to a large extent after that. In addition, since the delay is not taken into account, a considerable error might be caused between an originally expected delay and an actual one.
SUMMARY OF THE INVENTION
An object of the present invention is eliminating redundant registers as many as possible while taking the delay into account from the layout phase on such that chip area and power needed by a semiconductor integrated circuit can be both minimized.
To achieve this object, a register such as a flip-flop (i.e., a sequential circuit), which has nothing to do with the logic designed, is removed according to the present invention if a shortest total delay of a signal propagation path between a pair of registers preceding and succeeding that particular register exceeds a constraint time of a system clock signal.
Specifically, a first exemplary method according to the present invention is adapted to design a synchronous semiconductor integrated circuit, which includes first and second groups of logic devices and first, second and third registers. The output of the first register is connected to the input of the first group of logic devices. The input and output of the second register are connected to the output of the first group of logic devices and the input of the second group of logic devices, respectively. The input of the third register is connected to the output of the second group of logic devices. The method includes the step of a) adding together a shortest one of delays caused by respective signal propagation paths between the first and second registers and a shortest one of delays caused by respective signal propagation paths between the second and third registers to obtain a shortest total delay. If the shortest total delay is longer than a time obtained by subtracting one clock cycle time from a sum of constraint times defining respective signal propagation times between the first and second registers and between the second and third registers, then the method further includes the step of b) removing the second register and thereby connecting the first and second groups of logic devices together.
According to the first method, redundant registers are removable even from the layout phase on. That is to say, the redundant registers can be removed in various process steps succeeding the logical design phase, or in the layout phase in particular, and therefore chip area and power needed can be cut down. In addition, since the circuit can be downsized, the length of a test vector, which is exemplary test data, can also be shortened, thus improving test efficiency.
A second exemplary method according to the present invention is adapted to design a synchronous semiconductor integrated circuit, which includes first, second and third groups of logic devices and first, second, third and fourth registers. The output of the first register is connected to the input of the first group of logic devices. The input and output of the second register are connected to the output of the first group of logic devices and the input of the second group of logic devices, respectively. The input and output of the third register are connected to the output of the second group of logic devices and the input of the third group of logic devices, respectively. The input of the fourth register is connected to the output of the third group of logic devices. If a signal propagation path between the second and third registers is a multi-cycle path requiring a number of clock cycles to complete a predetermined operation, the method includes the steps of: a) partitioning the multi-cycle path into temporary single-cycle paths by inserting at least one temporary register between the second and third registers; b) adding together a shortest one of delays caused by respective signal propagation paths between the first and second registers and a shortest one of delays caused by respective signal propagation paths between the second and temporary registers to obtain a first shortest total delay; and c) adding together a shortest one of delays caused by respective signal propagation paths between the temporary and third registers and a shortest one of delays caused by respective signal propagation paths between the third and fourth registers to obtain a second shortest total delay. If the first shortest total delay is longer than a time obtained by subtracting one clock cycle time from a sum of constraint times defining respective signal propagation times between the first and second registers and between the second and temporary registers, then the method further includes the step of d) temporarily removing the second register. Alternatively, if the second shortest total delay is longer than a time obtained by subtracting one clock cycle time from a sum of constraint times defining respective signal propagation times between the temporary and third registers and between the third and fourth registers, then the method further includes the step of e) temporarily removing the third register. And if the number of the temporary registers inserted is found larger than the number of the registers removed as a result of comparison between these numbers, then the method further includes the step of f) removing the temporary registers inserted and returning the second or third register into the original position thereof to restore the multicycle path. Alternatively, if the number of the registers removed is found larger than the number of the registers inserted, then the method further includes the step of g) regarding the temporary single-cycle paths as verified single-cycle paths.
According to the second method, if the number of removable registers is larger than the number of registers inserted, then the multi-cycle path is partitioned into the verified single-cycle paths. Thus, there will be an increased number of optionally removable registers.
A third exemplary method according to the present invention is adapted to design a synchronous semiconductor integrated circuit, which includes first and second groups of logic devices and first, second and third registers. The output of the first register is connected to the input of the first group of logic devices. The input and output of the second register are connected to the output of the first group of logic devices
Ishibashi Noriko
Kurokawa Keiichi
Toyonaga Masahiko
Kik Phallaka
Smith Matthew
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