Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Layout generation
Reexamination Certificate
2008-05-09
2011-12-06
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Layout generation
C716S050000, C716S051000, C716S052000, C716S054000, C716S056000, C430S005000, C430S030000
Reexamination Certificate
active
08074188
ABSTRACT:
A method for designing a mask is disclosed. A chip region can be defined and reduced to form a parent dummy pattern. A mesh dummy pattern can be formed, and portions where the parent dummy pattern and the mesh dummy pattern overlap each other can be removed to form offspring dummy patterns.
REFERENCES:
patent: 5595843 (1997-01-01), Dao
patent: 6099992 (2000-08-01), Motoyama et al.
patent: 6421820 (2002-07-01), Mansfield et al.
patent: 2002/0087942 (2002-07-01), Kitada
patent: 2004/0197677 (2004-10-01), Kohle et al.
patent: 2006/0097399 (2006-05-01), Hatano et al.
patent: 2008/0121939 (2008-05-01), Murray et al.
patent: 10-256255 (1998-09-01), None
patent: 2000-338646 (2000-12-01), None
patent: 2001-324796 (2001-11-01), None
patent: 2004-294664 (2004-10-01), None
Cho Gab Hwan
Lee Sang Hee
Chiang Jack
Dongbu Hi-Tek Co., Ltd.
Nguyen Nha
Saliwanchik Lloyd & Eisenschenk
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