Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-17
2005-05-17
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06895564
ABSTRACT:
A design technique considering a peak current is provided for high-level design of systems including LSIs. A hardware model representing the trade-off relationship between a leak current and performance is prepared in advance for functional units constituting the system. In the hardware model, the relationship between performance tpd and a source-drain leak current Pleak is described with a threshold voltage Vth as a parameter, for example. By referring to the trade-off relationship, design conditions for the functional units are determined under evaluation of the performance and power consumption of the entire system.
REFERENCES:
patent: 4558234 (1985-12-01), Suzuki et al.
patent: 5831864 (1998-11-01), Raghunathan et al.
patent: 6043536 (2000-03-01), Numata et al.
patent: 6433584 (2002-08-01), Hatae
Han et al., “Gate Leakage Current Simulation by Boltzmann Transport Equation and ilts Dependence on the Gate Oxide Thickness”, Sep. 1999, IEEE International Conference on SISPAD, pp. 247-250.*
Ferre et al., “Characterization of Leakage Power in CMOS Technologies”, Sep. 1998, IEEE International Conference on Electronic, Circuits and Systems, Paper, vol. 2, pp. 185-188.*
Wang et al., “An Investigation of Power Delay Trade-Offs for Dual Vt CMOS Circuits”, Oct. 1999, IEEE International Conference on Computer Design, Paper, pp. 556-562.*
Bowman et al., “A Circuit-Level Perspective of the Optimum Gate Oxide Thickness”, Aug. 2001, IEEE Transactions on Electronic Devices, pp. 1800-1810.*
“From Miniaturization to Total Skill, Reconstruction of CMOS Strategy . . . ”, Nikkei Microdevices, pp. 118-121, Aug. 2000 (partial English translation).
Mizuno Hiroshi
Moriwaki Toshiyuki
Shinde Hiroki
Takahashi Mikawa
Lin Sun James
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Siek Vuthe
LandOfFree
Method for designing LSI system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for designing LSI system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for designing LSI system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3383139