Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-09-15
2001-10-09
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06301692
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to the improvement of a method for designing a layout of a semiconductor integrated circuit by the cell-based automatic arrangement and wiring and a method for verifying the timing of the designed semiconductor integrated circuit, and more particularly to a layout designing method and a timing verifying method which are also suitable for circuits using the pass-transistor logic as well as the CMOS logic, a semiconductor integrated circuit in which a circuit using the pass-transistor logic and a circuit using the CMOS logic are provided together, a layout designing method which utilizes the cell-based automatic arrangement and wiring of the semiconductor integrated circuit, and a semiconductor integrated circuit which is the most suitable for a reduction in voltage.
2. Background of the Art
In the prior art, the cell-based layout technique has been used as a method for designing the layout of a semiconductor integrated circuit and a method for verifying a timing. For the same cell-based layout technique, there are methods which are referred to as a gate array and a standard cell. In these methods, layouts having high density which are manually created are prepared for individual cells in advance, the connection between the cells is defined, and arrangement and wiring are performed on the cell level according to the connection so that the desired block layout of a logic circuit is created.
Referring to the timing verifying technique for the layout created on the cell base, a delay value for each cell is obtained by a circuit simulator or the like in advance, and is assigned to each logic gate to verify a timing.
In the cell-based designing technique according to the prior art described above, a cell which is based on a CMOS circuit is used very often for the following reason. In the CMOS circuit, the input signal of the cell is sent to only the gate terminal of a MOS transistor, and the gate terminal is divided into a source terminal and a drain terminal on a current basis. Consequently, the CMOS circuit is easily operated independently on a cell unit as electrical characteristics. Accordingly, the electrical characteristics can be held on the cell unit when performing layout design and timing verification.
Recently, a circuit using the pass-transistor logic which performs logical operation by sending an input signal to the drain terminal of a MOS transistor as well as the gate terminal thereof has been used in place of a complete CMOS circuit. In some cases, the circuit having the pass-transistor logic is superior to the complete CMOS circuit in respect of a decrease in area, a reduction in consumed power, an increase in speed and the like. These cases have been disclosed in Document 1: K. Yano, et al., “A 2.8-ns CMOS 16×16-b Multiplier Using Complementary Pass-Transistor Logic” (IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, pp. 388-395, April 1990), and Document 2: A. Parameswar, et al., “A High Speed, Low Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications” (Proceeding of IEEE 1994 Custom Integrated Circuits Conference, pp. 278 to 281) and the like.
The technique for designing the layout of the circuit using the pass-transistor logic has been disclosed in Document 3: K. Yano, et al., “Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs” (Proceeding of IEEE 1994 Custom Integrated Circuits Conference, pp. 603-606), Document 4: Y. Sasaki, et al., “Pass Transistor Based Gate Array Architecture” (1995 Symposium on VLSI Circuits Digest of Technical Papers, pp. 123-124), and the like. The designing method which has been proposed in the Document 3 utilizes the cell-based layout designing technique according to the prior art. More specifically, three kinds of cells of circuits using the pass-transistor logic which have a plurality of input pins are prepared, the assignment of each input pin (the form of signal application) is changed in the cell of each circuit using the pass-transistor logic to generate a lot of logics therein. The logics of the circuits which are given are assigned to the cells to be arranged and wired by an automatic arrangement and wiring tool according to the prior art. Thus, a block layout is obtained. The technique which has been proposed in the Document 4 uses the gate array technique. A pair of P- and N-channel type MOS transistors are laid all over the gate array according to the prior art. On the other hand, a substrate cell is used in which the number of N-channel type MOS transistors is greater than that of P-channel type MOS transistors based on the average pass-transistor logic, and the numbers of N- and P-channel type MOS transistors which are required for the amplifier of an output portion and a memory cell.
However, the layout designing technique of the circuit using the pass-transistor logic which has been disclosed in the Document 3 utilizes plural kinds (three kinds) of unit cells in which a small number of transistors form a cell. Consequently, various kinds of logics can be generated by the combination of the plural kinds of unit cells so that the degree of freedom of a logic type can be enhanced. However, the type of the unit cell is restricted to plural kinds (three kinds). For this reason, there is a case where the driving capability, the area and the like which are suitable for the circuit cannot be obtained when completing the layout so that circuit characteristics become unstable and the superiority such as a decrease in area, a reduction in consumed power, an increase in speed or the like of the pass-transistor logic is impeded.
It can be supposed that a lot of transistors form a cell so as to ensure the stabilization of the circuit characteristics and the superiority of the pass-transistor logic, for example. In this case, there is a defect that many kinds of cells should be prepared in advance so as to enhance the degree of freedom of the logic type. Not only the circuit using the pass-transistor logic but also the logic circuit using the complete CMOS circuit has the defect that many kinds of cells should be prepared. In other words, many kinds of cells should be prepared for the driving capability and the logic classification to create the optimum layout in the cell-based layout design of the logic circuit using the complete CMOS circuit.
In the logic circuit using the pass-transistor logic, when the load capacity in the circuit is changed depending on the self cell state, the delay characteristics of the circuit are varied. Furthermore, when the source and drain terminals of the transistor are connected to other cells through signal paths respectively, the delay characteristics of the circuit are varied depending on the state of the other cells.
According to the circuit using the pass-transistor logic, consequently, in the case where it is verified whether or not the created block layout satisfies the desired timing characteristics, correct timing verification cannot be performed even though the delay characteristics for each cell are given to the logic timing verifying circuit having the gate level according to the prior art so as to perform verification. On the other hand, in the case where the created layout is wholly verified by a circuit simulation, a very long computation time and a very large storage region are necessary, which is not practical.
The semiconductor integrated circuits using the pass-transistor logic according to the prior art which have been described in the Document 1 and the Document 2 are applied to specific arithmetic units such as an adder, a multiplier and the like so as to create a layout by manual design (custom design). Consequently, it is difficult to automatically design the random logic by using general logic synthesis and the like.
By the layout designing technique which has been disclosed in the Document 3 and the Document 4, the random logic can automatically be designed. However, in the case where all circuits are design
Kumashiro Shinichi
Mae Youichirou
Mizuno Hiroshi
Moriwaki Toshiyuki
Tanaka Yasuhiro
Garbowski Leigh Marie
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Smith Matthew
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