Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-07-01
2003-03-11
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06532581
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a method for designing a layout of a semiconductor device. More particularly, the present invention relates to a method for designing a layout in such a manner as to make the layout of an interconnection structure easily changeable if the specifications of the device have been changed. The present invention also relates to a storage medium having stored thereon a program for executing such a layout designing method, and further relates to a semiconductor device with an easily modifiable interconnection structure.
As the functionality and performance of various microelectronic devices have been tremendously improved and as the size thereof has been drastically reduced over the past few years, the necessity of developing semiconductor devices for particular users (i.e., application specific integrated circuits (ASICs)) in a short time has been rapidly increasing. In order to further shorten the ASIC development time, IC's with various types of arrangements, e.g., gate-array types and embedded-gate-array types, have been provided. An arrangement of the gate-array type is partially incorporated into an IC with the embedded-gate-array-type arrangement.
In an IC with the gate-array-type arrangement, a logic circuit is formed to satisfy the specifications designated by a particular user by interconnecting or routing a plurality of gates arranged in advance to form an array as a master slice. According to this designing method, the user's designated specifications can be met only by designing the interconnection structure. Thus, it is possible to reduce the development cost and time.
In an IC with the embedded-gate-array-type arrangement, the gate-array-type arrangement is partially incorporated.
Depending on whether or not its specifications have been determined, functional circuits (also called simply “components” or “cells” are classified into the two categories of: a fixed circuit section (including fixed components or cells); and a non-fixed circuit section (including non-fixed components or cells). A standard-cell-type arrangement is applied to the fixed circuit section, while the gate-array-type arrangement is applied to the non-fixed circuit section. After the specifications of the non-fixed circuit section have been determined, the gates, which have been formed like an array in the non-fixed circuit section, are routed as per the specifications determined. According to this designing method, fixed circuit sections, such as memory sections, can be fixed before the layout designing is started. Thus, to finish the overall circuit design, the designer has only to design the non-fixed circuit section, thus further shortening the development time. In addition, since the fixed circuit section may be implemented as an arrangement of standard cells, the number of components or cells that can be integrated per unit area increases compared to an IC with the gate-array-type arrangement. In other words, the area of a chip required for integrating the same number of components can be reduced. An LSI of the embedded-gate-array type is disclosed in U.S. Pat. No. 4,786,613, for example.
The meanings of basic terms as used in this specification will be defined with reference to
FIG. 20. A
“layout”
900
defines a geometric or topographic arrangement for an LSI. The layout
900
for an LSI includes a component (or cell) layout
920
defining a functional circuit (or cell), and an interconnection layout
940
defining an “interconnection”. The component layout
920
includes a plurality of component planar layouts
922
,
923
,
924
,
925
and
926
, which define n-well, active region, polysilicon layer, p
+
-type doped region and n
+
-type doped region, respectively. The interconnection layout
940
also includes a plurality of interconnection planar layouts
942
,
943
,
944
and
945
, which define contact holes, first set of interconnection lines, through holes and second set of interconnection lines, respectively. The “interconnection” includes not only interconnection lines within a plane, but also interlayer connections by way of through holes (or via holes). In fabricating a semiconductor device by ordinary photolithographic processes, a number of masks, corresponding to respective planar layouts, are produced.
However, no matter whether an IC is designed using the gate-array-type or embedded-gate-array-type arrangement, the time taken to define the layout design continues to increase with the increasing number of gates or interconnection layers provided. In addition, the cost and time taken to produce a mask is also increasing with such a complication of physical circuit design. A mask used to produce a fine-line pattern (e.g., with a design rule of 0.25 &mgr;m or less), in particular, is much more expensive than a conventional mask (e.g., with a design rule of 0.35 &mgr;m or more). Furthermore, along with an increase in number of layers in a multilevel interconnection structure, the number of masks required for fabricating a single semiconductor device is also considerably increasing (e.g., 6 or more masks are needed recently). Accordingly, such an increase in cost and time taken to produce the masks can now be regarded as a main factor increasing the cost and time taken to develop a semiconductor device.
Hereinafter, a conventional method for designing a layout for an LSI will be described with reference to FIG.
21
.
FIG. 21
is a flowchart illustrating a conventional method for designing a modified layout for an LSI, which has been once designed, but should have the circuit design (interconnection structure) thereof partially changed after that.
First, in Step S
1700
, a layout for the LSI is designed based on a netlist N
1
representing interconnection information according to initial specifications. At this point in time, an initial layout is produced according to the initial specifications. If the design need not be changed, then the initial layout is output and a mask (exactly, a set of masks) is produced based on the initial layout. The set of masks includes a plurality of masks associated with respective planar layouts included in the initial layout.
Next, in Step S
1710
, a netlist N
2
representing modified interconnection information is made to reflect the change in circuit design.
Then, in Step S
1720
, a new layout is designed for the LSI based on the netlist N
2
, thereby producing a modified layout according to the changed specifications. The modified layout is produced totally independent of the initial layout. For example, in an LSI with the gate-array-type arrangement, all the interconnections are rerouted.
Subsequently, in Step S
1730
, the modified layout, corresponding to the netlist N
2
, is output. And based on the modified layout output, the masks are produced again.
The prior art layout designing method, however, has the following drawbacks. Hereinafter, it will be described specifically what problems are caused if the conventional layout designing method shown in
FIG. 21
is applied to an LSI with the gate-array-type arrangement.
When the layout of the LSI with the gate-array-type arrangement is modified based on the netlist N
2
reflecting the changed specifications, all the interconnections are rerouted. Accordingly, the number of process steps and the number of masks, which are required for re-designing the layout, cannot be reduced. In other words, the time and cost taken to modify the layout cannot be reduced. If several masks have already been produced based on the initial layout when it turns out that the layout should be modified, then all of those masks should be discarded and new masks should be produced over again. Furthermore, if a wafer (i.e., a master slice) has already been introduced into the LSI production line at that point in time, then all the half-finished products should be thrown away.
For example, even when some minor changes should be made in input/output signal transmission lines or pull-up components for a power supply, all the masks ass
Toyonaga Masahiko
Tsuzuki Kazuo
Peabody LLP Nixon
Siek Vuthe
LandOfFree
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