Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-05-25
2003-12-23
Smith, Matthew (Department: 2825)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C716S030000, C716S030000, C716S030000, C716S030000, C703S014000, C703S015000, C703S016000, C703S017000
Reexamination Certificate
active
06668337
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of designing an integrated circuit such as a system LSI, and more particularly to design measures to reduce power consumption through the realization of a floorplan that incorporates a transaction analysis at an upper level.
In recent years, power consumption associated with enhancing functions and performance of integrated circuits such as a system LSI has been regarded as of importance. The reason is that the power consumption of integrated circuits significantly influence costs or the product value of battery, packages, and so on. This means there is an increasing need for a power consumption analysis for the sake of low power design.
Now, an integrated circuit such as a system LSI is designed along a large flow including system design, RTL design, floorplan synthesis, arrangement, and wiring/validation, being realized step by step. Then, after the arrangement and wiring of circuit elements are realized, it becomes possible to estimate (analyze) the power consumption of the integrated circuit. Here, letting C, f, and V stand for the capacitance, frequency, and voltage, respectively, the power consumption P is given by the following equation (1):
P=K·C·F·V
2
, (1)
where K is transition probability.
Of the parameters on the right side of the equation (1), the voltage V is determined by the design specifications. The frequency can be grasped at the stage of designing the functions and logic of the integrated circuit. The capacitance C can be estimated from the areas of the individual devices and those of the wires on the integrated circuit when the arrangement and wiring are determined.
Thus, the estimation of power consumption of conventional integrated circuits at the designing stage is typically performed after the completion of the temporary arrangement and wiring, or actual arrangement and wiring. After the power consumption is estimated, designing is repeated for optimization so that integrated circuits of low power consumption type are designed finally.
With the advent of system LSIs and other large-scale integrated circuits as in recent years, however, considerable amounts of time have come to be expended not only in the optimization of power consumption but also in the estimation of power consumption. In particular, image-handling applications with enormous input data are on the increase recently. Besides, identical circuits vary in power consumption while executing different applications. On that account, the power consumption analysis in the automatic designing of integrated circuits has become increasingly complicated, with a tendency of the period involved in the analysis to be longer. Consequently, at the moment, any technique actually available for the power consumption analysis at the automatic designing stage is not proposed yet.
Then, power consumption could be estimated at the upstream side before the arrangement and wiring so that the power consumption estimation at the designing stage is performed with higher efficiency. This would require only that each parameter on the right side of the equation (1) be estimable at the upstream designing stage.
Under present circumstances, however, there is provided no means appropriate for the upstream-side estimation of the capacitance C among the parameters in the equation (1). At this point, the present inventors have reached a conception of utilizing a transaction analytical technology for analyzing power consumption.
Conventionally, the transaction analytical technology has been used chiefly in designing a large-scale network system. In a network system, individual terminals connected to fragmented communication networks actively utilize the communication networks, basically without any mechanism for integrated control over the communication networks. Accordingly, when constructing a network system, it has been necessary to examine the throughput of the communication networks under assumed situations of utilization. It is the transaction analytical technology that has been used as a method of “assuming the situations of utilization.”
Nevertheless, the conventional transaction analysis includes no function of validating the logic of data communicated within such a large system. The conventional transaction analytical technology is an analytical technology to grasp only the occurrence, flow, and disappearance of transactions for the sake of analyzing the transactions that cause a decrease in throughput, or the degree of congestion of processes.
Meanwhile, as devices and circuit elements get finer with the recent advances of process technologies, LSIs are growing in functionality and performance. As a result, it has become increasingly difficult to develop multifunction, high-performance LSIs by market-demanded time without introducing reuse design techniques for making effective use of existing parts into LSI design. An LSI constructed through such reuse design techniques may be regarded as a network system. That is, in the LSI, reused parts with desired functions are connected to the backbone wiring, or a communication network within the LSI. These reused parts correspond to terminals. Then, the individual reused parts actively utilize the backbone wiring to transmit data to each other for processing, to achieve their desired objectives.
Nonetheless, the transaction analytical technology has not been used for power consumption analysis heretofore. The following are two possible reasons for this. One is the significance of power consumption, and the other lies in the content of the transaction processing.
Initially, description will be given of the implication of power consumption. In network systems, the terminals connected to communication networks are dispersed physically. Besides, the communication networks for connecting the terminals are made of materials having lower electric resistances. Therefore, in the network systems, the power consumption of the entire systems has mattered little. That is, there has been no motivation to use the transaction analytical technology for analyzing power consumption.
Now, turn to the content of the transaction processing. In network systems, the transaction amount output from a function for performing certain processing depends on a transaction amount input and the frequency of data input. On the other hand, a system LSI performs not only such processing as described above, but also compression, expansion, and other processing in which the transaction amount to be output may vary greatly with input data properties. Introducing these transaction amount variations resulting from differences in data property into the analysis of power consumption requires some model, whereas such a model itself is not yet in existence.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of designing an integrated circuit, in which a model capable of utilizing a transaction analytical technology for analyzing power consumption can be established to allow easy and efficient consideration for lower power consumption.
A method of designing an integrated circuit in the present invention comprises the step of performing a transaction analysis by using a transaction analyzing model including a database for storing a transaction amount in an integrated circuit to be designed, the transaction amount being expressed as events in a statistical distribution.
According to this method, a high-speed analysis can be made in performing a power consumption estimation within a realistic time with an eye to the fact that transactions well reflect the frequencies of operations in an integrated circuit.
The transaction analyzing model is to select a plurality of transaction amounts and frequencies of occurrence based on the statistical distribution. This allows a selection for efficient use of design resources.
The database of the transaction analyzing model stores a normal distribution as the statistical distribution. Therefore, the transaction analyzing model can be created easily.
The transaction analysi
Motohara Akira
Ogawa Osamu
Takahashi Miwaka
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Rossoshek Yelena
Smith Matthew
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