Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-22
2003-09-09
Lam, Tuan T. (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06618848
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for designing a circuit layout of memory devices, and more particularly to a method for designing a circuit layout of non-neighboring metal bit lines to reduce coupling effect.
2. Description of the Prior Art
A memory device for storing data has a great significance in a data processing system. Memory devices are largely grouped into volatile memory devices, such as random access memories (RAM), whose information is destroyed when power is interrupted and non-volatile memory devices, such as read-only memories (ROM), whose information is retained despite the interruption of power. Particularly, memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. These devices provide an indication of the data which is stored therein by providing an output electric signal. A device called a sense amplifier is used for detecting the signal and for determining the logical content thereof.
In general, sense amplifiers determine the logical value stored in a cell by comparing the output of the cell with a reference signal. If the output is above the reference signal, the cell is determined to be erased (with a logical value of 1), and if the output is below the reference signal, the cell is determined to be programmed (with a logical value of 0). The reference signal level is typically set as a voltage level between the expected erased and programmed voltage levels which is sufficiently far from both expected voltage levels so that noise on the output will not cause false results.
Memory devices such as read-only memories ordinarily comprise an array of memory cells. Each column in the array is connected to a bit line (BL), and each row in the array is connected to a word line (WL). Data is read by placing electric signals on the appropriate word lines and bit lines via address decoders. In a read procedure, one of the two selected bit lines is defined as a source and the other is defined as a drain from which the content of the cell will be read. The read-out operation is a process of comparing amounts of currents flowing through a reference cell and a memory cell by using a sense amplifier after making currents flow through the reference cell and a selected memory cell and outputting data output from the sense amplifier to a data buffer.
However, as the density of integration gets higher and higher, the distance between adjacent bit lines has become closer and closer. The distance between two adjacent metal bit lines is too close when cell size continuously shrinks, thus creating cross talk problems. That is to say, coupling which occurs due to capacitance between adjacent bit lines is becoming more and more significant and non-negligible. Accordingly, the portion of the relevant data signal (programmed or erased) within the overall detected signal is significantly small. The detected signal is usually less than 100 mV, but the variation of the signal caused by the bit line coupling is within the range of several 10s mV. To reduce the coupling between adjacent bit lines, whether by extending the distance between adjacent bit lines, which also enlarges the required space of layout in the integrated circuit), or by staggering the operation time of adjacent bit lines, which prolongs the operation time, is a trade off. Hence, the recurring task in memory design is to take steps during layout of the memory to reduce metal bit line coupling.
Referring to
FIG. 1
, the conventional memory array
100
has a multiplicity of cells
110
which are organized into columns and rows. The memory array
100
contains “m” rows of cells
110
, wherein the variable “i” represents the i'th row. The “i” and “m” variables will also be used in conjunction with “WL” to designate the word lines connecting to the gates of the i'th and m'th rows of cells
110
, respectively. The memory array
100
also contains “n” columns of cells
110
, wherein the variable “j” represents the j'th column. The “j” and “n” variables are also used in conjunction with “BL” to designate the bit lines connecting the drains/sources of the j'th and n'th column of cells
110
, respectively. Using these designations, a particular cell in the memory array is designated as C(row, column), wherein C(i, j) is the cell in the i'th row and the j'th column. Two adjacent bit lines BLj and BLj+1 are used during the read-out operation of cell, C(i, j). That is to say, the cell layout is well corresponding to the circuit layout of metal bit lines in the design of the conventional memory array. In the sensing operation of the conventional memory array, two adjacent bit lines are usually used, and the coupling effect induced by the closeness of two adjacent bit lines becomes a problem in the operation.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for designing a circuit layout of non-neighboring metal bit lines to reduce coupling effect in sensing operation. The present invention takes steps, during layout of the memory device, to design a non-neighboring bit line layout. The non-neighboring bit line layout reduces bit line coupling effect that substantially prevents from false results due to bit line coupling in the read-out operation of a memory device without any trade off of integrated density and time prolongation.
It is another object of this invention that bit line coupling effect is reduced or eliminated by designing a circuit layout of non-neighboring metal bit lines.
It is a further object of this invention that bit line coupling effect is reduced without increasing the circuit layout space.
A method for designing a circuit layout of non-neighboring bit lines to reduce coupling effect in sensing operation is disclosed. The method reassigns the sequence of metal bit lines in layout design corresponding to the logical sequence of metal bit lines by separating adjacent bit lines used in the sensing operation of the memory array. In one embodiment, the method comprises a step of providing a memory array having a plurality of bit lines arranged sequentially, wherein every two adjacent bit lines are paired using in sensing operation of a memory cell in the memory array. Then, a first pair of bit lines is permuted with each other in layout design, whereby the bit lines adjacent to the permuted pair of bit lines are not arranged sequentially in layout. Thus, coupling effect is reduced by the non-neighboring bit line layout of the memory array in sensing operation. The method further comprises assigning a second pair of the bit lines permuted with each other. The coupling effect which is induced by the permuted pair of bit lines can be reduced by extending the layout space between the permuted pair of bit lines or, in other word, by shrinking the layout space between two adjacent non-paired bit lines.
In another embodiment, a method for designing a circuit layout of non-neighboring bit lines to reduce coupling effect in a sensing operation is provided. The method comprising a step of providing a memory array having a plurality of bit lines arranged sequentially, wherein every two adjacent bit lines are paired in the sensing operation of a memory cell in the memory array. Then, in a layout design, a first pair of bit lines is separated by inserting one of a second pair of the bit lines into the first pair of bite lines. Thus, the coupling effect is reduced by separating logical adjacent bit lines in the non-neighboring bit line layout of the memory array in the sensing operation. The method further comprises the step of shrinking the layout space between the separated first pair of bit lines. That is to say, the layout space between two adjacent non-paired bit lines is reduced. The method further comprises inserting one of a third pair of bit lines into the separated first pair of bit lines.
REFERENCES:
patent: 5818786 (1998-10-01), Yoneda
patent: 6353569 (2002-03-01), Mizuno et al.
Chen Han-Sung
Hung Chun-Hsiung
Liao Kuo-Yu
Lin Yung-Feng
Liou Ho-Chun
Dickinson Wright PLLC
Lam Tuan T.
Macronix International Co. Ltd.
Nguyen Linh
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