Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-09-16
2004-11-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06823499
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit designs. More particularly, the present invention relates to a method for designing Application Specific Integrated Circuits (ASICs) structure.
BACKGROUND OF THE INVENTION
An ASIC is a semiconductor device designed especially for a particular application or use. The ASIC technology includes two major categories: Array-Based and Cell-Based. Array-Based ASICs configure a customer's design at the metal layers, whereas Cell-Based ASICs are uniquely fabricated at all layers of the silicon process including the diffusion layers. Here, a “layer” means a mask layer. Here, “masks” are the shapes used for processing features in a particular process step of integrated circuit production.
Array-Based ASIC products include an array of repeating identical base cells (or “gates”) in a core region of a semiconductor chip. Each of such base cells contains the same predetermined number and arrangement of transistors. For example, a “gate” may be a two-input NAND gate including four CMOS transistors, two n-channel transistors and two p-channel transistors. Gate arrays contain more gates than will be used to implement the custom design because of their general-purpose nature. In conventional Array-Based architectures, all metal layers from Metal-1 layer and above (back-end layers) are processed to complete a design definition. The diffusion layers (front-end layers) have already been completed by the silicon foundry, as a pre-constructed general-purpose silicon, before implementing the customer design. Array-Based ASICs offer fast implementation of a customer's logic design onto a piece of silicon because of the smaller number of masks (and attendant process steps) required to define the specific function of the chip.
Cell-Based ASICs generally employ many different base cells, as opposed to a single repeating base cell. Typically, these various base cells have different sizes, shapes, transistor arrangements, etc., and the cells can be located anywhere on the die in accordance with a given circuit design. Because base cell choice and their arrangement are fully customized to a given integrated circuit design, Cell-Based ASICs use available chip space more efficiently than Array-Based ASICs. Cell-Based ASICs are uniquely fabricated at all layers of the silicon process including the diffusion layers, and thus one design is very difficult to modify to perform another function or customer design. Since all masks are unique and customized per design, it takes significant time to implement a specific circuit design or make any changes thereto.
The ASIC technology also includes Application Specific Standard Products (ASSPs) and Embedded Arrays. ASSPs are also full custom chips, but they have been designed and defined by the ASSP vendor, rather than by a particular customer, so as to fit specific system requirements and may be used by one or many customers. Embedded Array technology is a hybrid of Array-Based and Cell-Based architectures. In Embedded Array products, large memories and/or cores are first embedded into a circuit design and then the area around the large cells is filled with standard gate array transistors (masterslice structure). The chip is customized because the customer design defines the large cells and their locations. However, the random logic area is designed and laid out using the standard gate array areas. In an Embedded Array design, all masks are still customized for a specific circuit design, and if some design changes are made, all of the metal layers, including the top metal layers, are used to implement the given change.
In order to implement a given circuit design or changes thereto in a conventional Array-Based or Embedded Array ASIC architecture, a full set of metal masks must be manufactured and the full process steps in the back end from contact layer upwards must be processed. As process technologies employ a larger number of metal layers and/or tighter critical dimensions, however, it is becoming very costly and time-consuming to change the entire mask set and perform the entire metalization process for all of the metal layers. This also diminishes the advantages of the gate array products, including Array-Based and Embedded Array ASICs, over Cell-Based products., However, since today's circuit systems have short lifetimes, time-to-market and cost for manufacturing can be significantly important considerations.
On the other hand, a metal-only Engineering Change Order (ECO) also provides for implementing changes in a customer design using metal layers. However, the conventional process of metal-only ECO is not capable of implementing a new circuit design or major design changes, and is typically used to implement very limited design changes such as fixing bugs of an existing circuit design.
Accordingly, it would be desirable to provide a method for designing ASIC structures that reduces the mask costs and improves the turn around time, yet providing sufficient accommodation of customer designs and design changes.
BRIEF DESCRIPTION OF THE INVENTION
A method for designing an Application Specific Integrated Circuit (ASIC) structure on a semiconductor substrate, includes (a) defining a class of circuit designs, the class having a common design part shared within the class and a custom design part variable for individual designs in the class, (b) allocating a set of bottom layers and a set of top metal layers to implement the common design part, the allocated sets of bottom layers and top metal layers having a fixed pattern for the class, and (c) implementing the custom design part using metal layers above the allocated set of bottom layers and below the allocated set of top metal layers. The method may further includes characterizing the ASIC for the common design using the fixed patterns of the allocated set of bottom layers and the allocated set of top metal layers.
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Delp Gary
Vasishta Ronnie
Dinh Paul
LSI Logic Corporation
Siek Vuthe
Thelen Reid & Priest LLP
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