Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-10-18
2004-03-09
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06704910
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of semiconductor integrated circuits. The invention particularly relates to methods for designing and manufacturing integrated circuits, and to integrated circuits so produced.
BACKGROUND OF THE INVENTION
The creation of a new semiconductor integrated circuit includes the following activities. Integrated circuit designers start with some description of the circuit's function. From this description or specification, the designers generate a design netlist. The design netlist contains a list of the components of the circuit and also contains a list of the interconnections between those components. The design netlist also contains a list of I/O buffers with their associated bonding pads and their connections to the other components. The designers then apply electronic design automation (EDA) tools to the netlist to create the physical layout of the components as they will appear in the integrated circuit die. With present day semiconductor technology, and using 0.25 micron feature size, designers can put up to 2 million logic gates and up to 250 input/output (I/O) ports on a 7 mm by 7 mm die. The majority of designs at this date, however, contain only about 50K to 80K gates of logic and about 200 I/O's.
The physical layout of a 0.25 &mgr;m design consists of a set of about 18 to 26 unique mask levels. This information is supplied to a mask-making facility where the information is used to generate a set of glass masks for that particular design.
The mask set is then sent to a wafer fabrication facility where the mask set is applied to process a batch of about 20 semiconductor wafers. After the wafers have been completely processed, they are sent to wafer electrical test where dice that do not meet specification are inked or otherwise marked reject. The tested wafers are then sawn into individual dice, each die containing one integrated circuit. The dice are packaged and then electrically tested in a procedure known generally as final test. Based on the wafer electrical probe test results and the final test results, it may be necessary to correct the design and generate a second generation design with a second generation mask set. The costs associated with the design and prototyping activities just described are quite substantial.
There are several methods in use currently that aim to share some of the costs of the activities mentioned above.
So-called Gate Arrays provide one method of sharing costs. At this date, a mask set may have from 18 to 26 levels in a typical 0.25 micron CMOS process. In the gate array method, the first two thirds of these mask levels are common to all designs. Only the final one third of the mask levels are specific to each new design. The benefit here is that the first two thirds of the masks do not have to be designed and made anew for each new integrated circuit design and also that wafer fabrication time for a new design can be reduced by processing wafers in advance through the common masks and holding the partially processed wafers in stock ready to continue prototype processing through the last one third of the mask layers.
There are disadvantages to the gate array approach. Since the basic transistors have to be fabricated ahead of time, they all have to be of standard fixed sizes. Without the flexibility of being able to use varying transistor sizes in different parts of the new circuit design and of adding user-specific circuit components, the integrated circuit size increases and the performance degrades. The engineering costs to generate each design layout and to personalize the last one third of the mask layers are incurred for each design and are not sharable. Another disadvantage is the inability to incorporate custom-designed blocks such as analog cells or true static random access memory (SRAM) blocks. With the increasing levels of integration that are now available in deep submicron process technologies, almost all designs made today in 0.25 micron or better technologies incorporate some amount of SRAM.
Another approach to sharing prototyping costs is known as the multi-project wafer approach. In the multi-project approach, several projects, or integrated circuit designs, are combined in one mask set. Each design has its own bonding pads and input/output buffers located around the periphery of that design. In this approach, certain procurement costs are shared between the different designs that are included in the one mask set. If different users own the different designs on a given mask set, then the mask cost and wafer fabrication cost is reduced for each user. There are several organizations now running multi-project wafer programs. Among these is MOSIS, a not-for-profit organization located in southern California.
The multi-project wafer approach has some disadvantages. For example, since the several different designs in a multi-project die have their own unique bonding pads, probe testing at the wafer level is difficult in a production environment. Assembly of these designs into integrated circuit packages is difficult because of complications in the wafer sawing process. When a semiconductor wafer is sawed into dice, the entire wafer has to be sawed at a fixed indexing increment. In the multi-project approach, if there are 10 designs of different die sizes on the wafer, the saw is indexed to yield dice containing 1 of the designs, and thus the saw destroys other designs. Also, if one of the designs is to go into production, a new mask set will need to be made, containing only that design. Cost sharing is possible only at the prototyping stage and not at the production stage.
Therefore, there is a need for an integrated circuit architecture that provides multiple integrated circuit designs in a single die, wherein all of the designs on a die are testable at wafer probe test, and wherein all of the designs survive the wafer sawing operation and the package assembly operation, thus providing complete cost sharing from design through final test. There is also a need for an integrated circuit architecture that, during assembly, allows any number of the designs to be made accessible or inaccessible in the packaged device. There is also a need for a design method that produces this integrated circuit architecture.
OBJECTS AND ADVANTAGES
It is an object of the present invention to provide a multi-design integrated circuit die that contains multiple integrated circuit designs and a set of bonding pads that is shared by the different designs on the die.
It is an object of the present invention to provide a multi-design integrated circuit, in which the multiple circuit designs in the integrated circuit can be probe tested via one set of shared bonding pads.
It is a further object of the present invention to provide a multi-design integrated circuit die that has bonding pads located, not around each design, but rather in an area of the die near the periphery of the multi-design die.
It is a further object of the present invention to provide a multi-design integrated circuit die, in which, after the die has been assembled into an integrated circuit package, any of the circuit designs can be accessed.
It is a further object of the present invention to provide a design method for designing multi-design integrated circuits.
It is a further object of the present invention to provide an automated design method for designing multi-design integrated circuits.
It is a further object of the present invention to provide an automated design method for designing a multi-design integrated circuit die that not only provides cost sharing during prototyping but that is also production-ready.
It is a further object of the present invention to provide an automated design method for designing a multi-design integrated circuit die that allows the designer freedom to customize the individual components in each design within the integrated circuit die.
SUMMARY
The objects and advantages of the present invention are obtained by generating a multi-design netlist that contains and is a combination of
Lumen Intellectual Property Services Inc.
QualCore Logic, Inc.
Siek Vuthe
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