Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-06
2003-04-15
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C174S034000, C174S261000
Reexamination Certificate
active
06550037
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for designing a decoupling circuit and, more particularly, to a method suitable for designing a decoupling circuit for each of power source lines (power supply lines) of a plurality of semiconductor integrated circuits (LSIs) mounted on a common multilayer printed circuit board.
(b) Description of the Related Art
Digital circuits generally generate unwanted electromagnetic field emissions (EMIs) from multilayer printed circuit boards. Most of the EMIs are generated from the signal transmission lines as well as from the power source lines constituting resonators together with the ground layer of the PCB. This fact necessitates employment of a counter measure for the EMIs in the power source line. It is generally effective to use a decoupling circuit for suppressing the EMIs.
For instance, in Patent Publications JP-A-10-97560 and JP-A-11-15870, effective areas for disposing capacitors therein for suppressing the EMIs are depicted on a drawing for the layout of the printed circuit board. The methods described therein, however, have a disadvantage in that the design for selecting the capacitance of the capacitors cannot be specifically determined. In particular, in a design for designing a power source system including a main source line and a plurality of branch source lines each disposed for a corresponding LSI, most part of the higher-frequency current components in the operational current for driving the LSI is supplied from the decoupling capacitors, and the electric charge supplied therefrom differs depending on the circuit configurations and the operations of the internals of the LSIs. This means that selection of the decoupling capacitor for each LSI is preferably conducted for each of the LSIs while considering the characteristics of the each of the LSIs.
However, even if the circuit configuration of the LSI is known, the technique for determining the decoupling capacitor from the circuit configurations is vet to be determined. In short, there is no known design theory by which the circuit designers or users specifically determine the decoupling capacitor. In addition, for a larger number of LSIs disposed on a printed circuit board, it costs a larger amount of time to determine the decoupling capacitors for the respective LSIs.
In a technique such as described in JP-A-9-139573, a planar power source layer conventionally used for the printed circuit board is configured as respective source lines each having a specific width to thereby increase the impedance of the source line for supplying electric power to a corresponding LSI in a higher frequency range. This impedes to some extent higher-frequency current components from transferring through the source lines on the printed circuit board, whereby the electromagnetic field emission from the power source line is suppressed.
In the described technique, it is necessary to determine the length of the power source line, differently from the case of the planar source layer, because the power source line on the printed circuit board should have as small a length as possible in view of the restriction from the practical size etc. of the printed circuit board. However, the technique for determining the length of the source line is yet to be established. In view of the EMI reduction, a larger capacitance of the decoupling capacitor and a larger impedance of the source line on the printed circuit board are preferable due to a higher efficiency of decoupling.
For suppressing the higher-frequency current components flowing through the source line on the printed circuit board, it is also effective to determine the inductance of the source line on the printed circuit board for the object LSI based on the characteristics of the object LSI as well as determining the decoupling capacitor as described above. This is because the higher-frequency current components flowing through the source line depend on the configuration and the circuit scale of the LSI. The design for layout of the source lines requires a large amount of design work in view of the large number of LSIs mounted on the printed circuit board
SUMMARY OF THE INVENTION
In view of the above problems in the conventional technique, it is an object of the present invention to provide a method for power source decoupling in a printed circuit board mounting thereon a plurality of LSIs, which is capable of allowing reduction of unwanted electromagnetic field emission from the source lines while reducing the amount of design work for the decoupling circuit.
The present invention provides a method for designing a decoupling circuit for a source line of a LSI to be disposed on a printed circuit board. The method comprises the steps of determining a capacitance of a decoupling capacitor based on electric charge necessary for driving the LSI in a specified period and an allowable voltage fluctuation of a source voltage at a source terminal of the LSI, and determining an inductance of the source line based on an impedance of the decoupling capacitor and a multiplexing ratio of the source current of the LSI by the decoupling capacitor.
In accordance with the method of the present invention, a decoupling circuit can be designed for the source line of the LSI with a reduced design work. The resultant decoupling circuit has a decoupling circuit which allows the source line and the decoupling capacitor to supply the electric charge necessary for driving the LSI and an inductance of the source line which allows an effective source decoupling for the LSI.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
REFERENCES:
patent: 6359237 (2002-03-01), Tohya et al.
patent: 6365828 (2002-04-01), Kinoshia et al.
patent: 09-139573 (1997-05-01), None
patent: 10-97560 (1998-04-01), None
patent: 11-15870 (1999-01-01), None
Ando Noriaki
Irino Hitoshi
Tohya Hirokazu
Wabuka Hiroshi
Rossoshek H
Smith Matthew
LandOfFree
Method for designing a decoupling circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for designing a decoupling circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for designing a decoupling circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3094923