Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2000-11-28
2004-05-18
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C710S009000
Reexamination Certificate
active
06738920
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer systems in which a plurality of components interact with one another in a manner which requires that each component know its relationship to the other components. That relationship may be physical, as in a daisy chain connection of components, or it may be virtual, as in the assignment of addresses to components on a communication bus. The present invention relates in particular to how each component determines that relationship.
BACKGROUND OF THE INVENTION
A control system for complex equipment often is divided into subsections which control different portions of the equipment. For example, a large material handling system may be divided into a cascade of conveyor sections with a separate microcomputer controller governing the performance of each section. In order for the separate sections to operate in a cooperative manner, the microcomputer controllers have to communicate among one another.
That communication may be accomplished through conductors which interconnect the controllers in a daisy chain. In this communication scheme a given controller is able to send and receive messages to and from only the immediately adjacent controllers in the chain. Messages can be relayed along the daisy chain from one controller to the next one. Nevertheless to properly control the flow of objects along the conveyor system, it is important that each controller know its relative location, or address, along the conveyor and thus along the daisy chain. Thus during installation, the address of each controller is designated, such as by a technician setting a number of switches in each controller.
In another configuration, a shared communication bus extends along the conveyor system and every controller in connected to the bus. Each controller is assigned a unique bus address. When one controller desires to communicate with another controller, a message containing the address of the intended recipient is transmitted over the communication bus.
The greater the number of devices that must communicate with each other in both these communication techniques, the greater the likelihood that one of the devices may be configured with an incorrect address. Accordingly it is desirable to provide an apparatus and method by which the address of each device can be set automatically.
SUMMARY OF THE INVENTION
The present method assigns addresses to a series of modules connected to a common conductor. The series has an initial module and a terminal module at opposite ends with at least one intermediate module there between.
In response to an occurrence of a predefined event, such as power-up of the modules, a first signal is sent via the common conductor to the modules. Upon receiving the first signal, a first timer is started within each intermediate module and within the terminal module. A predefined period after receiving the first signal, the initial module sends a timing signal to an adjacent module in the series. When an intermediate module receives a timing signal, the respective module starts a second timer and a predefined period thereafter sends a timing signal to an adjacent module in the series. Upon receiving a timing signal, the terminal module sends a second signal via the common conductor.
In response to receiving the second signal, each of the intermediate modules derives an address in response to its first timer and its second timer, and the terminal module derives an address from its first timer. In the preferred embodiment of the present method, each intermediate module derives the address according to the expression:
ADDRESS=(
T
1
−
T
2
)/
N
where T
1
is a value from the first timer of the respective intermediate module, T
2
is a value from the second timer of the respective intermediate module, and N is the predefined period. In that preferred embodiment, the terminal module derives the address according to the expression:
ADDRESS=
T
1
/
N
where T
1
is a value from the first timer of the terminal module and N is the predefined period.
REFERENCES:
patent: 4730251 (1988-03-01), Aakre et al.
patent: 4773005 (1988-09-01), Sullivan
patent: 5204669 (1993-04-01), Dorfe et al.
patent: 5262771 (1993-11-01), Hermann et al.
patent: 5404460 (1995-04-01), Thomsen et al.
patent: 5452424 (1995-09-01), Goeppel
patent: 5495575 (1996-02-01), Hermann et al.
patent: 5914957 (1999-06-01), Dean et al.
patent: WO 94/16382 (1994-07-01), None
Chandrasekhar P.
Haas George E.
Lee Thomas
Quarles & Brady LLP
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