Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-08-02
2001-07-24
Everhart, Caridad (Department: 7812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S680000, C438S648000, C427S250000
Reexamination Certificate
active
06265312
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to the fabrication of integrated circuits and in particular to the deposition of metallizations in an integrated circuit. Still more particularly, the present invention relates to a method of depositing tungsten via fill stacks that provides an improved tungsten film stack profile across a wafer through the inclusion of a post-nucleation pump down step.
2. Description of the Related Art
Achieving performance enhancements in complementary metal-oxide-semiconductor (CMOS) technology requires both improved device performance and high circuit density. For current and future CMOS geometries, which obtain high circuit density in part by implementing multiple circuit layers, the formation of multi-level interconnects is an important stage of integrated circuit (IC) fabrication.
Tungsten (W) is widely utilized to interconnect various layers of metal in ICs. Tungsten metallizations are typically formed by chemical vapor deposition (CVD), which permits reliable filling of high aspect ratio contacts and vias and which yields interconnections that are resistant to electromigration. A conventional tungsten CVD process includes two principal steps: first, a nucleation step in which WF
6
is reduced by SiH
4
and H
2
at low pressure, and second, a deposition step in which a W (tungsten) fill is deposited at high pressure. It is well-known that nitrogen (N
2
) is employed as the carrier gas for SiH
4
and can improve the reflectance (i.e., surface smoothness) of the deposited tungsten film by reducing the film grain size.
Referring now to
FIG. 1
, there is depicted a cross-sectional view of a portion of a wafer substrate including a conventionally formed tungsten plug. Wafer substrate
10
has a embedded metallization layer
12
that is electrically connected to features (e.g., transistor
8
) in a lower layer by a tungsten plug
14
and can be electrically connected to features formed over two interlayer dielectric (ILD) layers
16
and
18
by a second tungsten plug
20
. As shown, second tungsten plug
20
includes a number of layers, the first of which is a liner
22
comprising a 400 Å layer
24
of Ti and a 1000 Å layer
26
of TiN. After the liner deposition, the wafers are placed in the tungsten CVD tool. A tungsten fill stack is then deposited that includes a nucleation layer
27
of 800 Å, which is formed by reducing WF
6
with SiH
4
(at a 2:1 mixture) and H
2
under a low pressure of approximately 4.5 Torr. Following a brief stabilization period, a 7200 Å tungsten fill layer
28
is deposited under a high pressure of approximately 90 Torr to complete the tungsten fill stack.
If the tungsten deposition is successful, the profile of the tungsten plugs will vary across a wafer somewhat uniformly from thicker at the edges to thinner at the center. A wafer having this desirable tungsten plug profile is shown in plan view in FIG.
2
A. As illustrated, wafer
40
is generally circular, with a notch
42
at one edge. The topography of the tungsten deposition on the surface of wafer
40
is indicated by concentric delineations
48
as varying substantially uniformly between thicker at edge region
44
and thinner at center region
46
.
If on the other hand, film instability is experienced during the tungsten deposition, the tungsten plugs will have an undesirable profile in which the tungsten deposition is thicker at the center of the wafer and thinner at the edges of the wafer. A wafer having this undesirable tungsten deposition profile is shown in plan view in FIG.
2
B. As illustrated, wafer
50
is generally circular, with a notch
52
at one edge. The topography of the tungsten deposition on the surface of wafer
50
is indicated by delineations
58
as varying non-uniformly between thinner at edge region
54
and thicker at center region
56
.
Following the tungsten deposition, the wafer is typically subjected to either chemical etching or chemical-mechanical polishing (CMP) to remove excess tungsten. If the tungsten plugs have the desirable profile illustrated in
FIG. 2A
, then an etch back process would stop on liner
22
, and a CMP process would stop on ILD
18
, resulting in either case in a planar profile across the wafer from center to edge. If, however, the tungsten deposition results in the undesirable profile depicted in
FIG. 2B
, then a number of process problems can result from either an etch back or CMP process. In particular, tungsten that should be removed can remain adjacent to vias in the center of the wafer, while the wafer can be thinned towards the edges more than it should be. As a result, for an etch back process, fluorine ions remaining from the nucleation step can form SF
6
during the etch back process and attack liner
22
. Consequently, TiF
3
may be formed, which is a well-known source of interconnect reliability problems. If, on the other hand, a CMP process is performed, ILD layer
18
will be thinner at the edge of the wafer than at the center, possibly resulting in dielectric breakdown, and recesses in the tungsten fill plugs may be created, possibly causing severe current leakage problems.
SUMMARY OF THE INVENTION
In order to avoid the process integration problems described above, it is important that a desirable tungsten film stack profile be obtained for each wafer that is processed. The present invention reliably achieves a desirable film stack profile for each wafer through an improved tungsten film stack deposition process that includes a post-nucleation pump down step.
According to the present invention, a tungsten film stack is formed on a wafer using a deposition chamber by first depositing a nucleation on the wafer in the presence of a carrier gas, such as nitrogen. Following deposition of the nucleation, excess carrier gas is evacuated from the deposition chamber. Then, following evacuation of the excess carrier gas, a tungsten fill is deposited over the nucleation.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5956609 (1999-09-01), Lee et al.
patent: 6066366 (1999-09-01), Berenbaum et al.
Melosky Stephen John
Sidhwa Ardeshir Jehangir
Everhart Caridad
Galanthay Theodore E.
Jorgenson Lisa K.
STMicroelectronics Inc.
Venglarik Daniel E.
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