Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-06-01
2001-09-18
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S626000, C438S692000, C438S787000, C438S788000, C438S791000, C438S792000, C427S579000, C427S255370
Reexamination Certificate
active
06291367
ABSTRACT:
DESCRIPTION
1. Technical Field
The present invention relates generally to the field of silicon processing, and more specifically to a method of forming an interlevel dielectric on a semiconductor wafer.
2. Background Art
In the construction of a semiconductor device, many conductive device regions or layers are formed on a semiconductor substrate. In order to isolate these layers or regions, an interlevel dielectric layer is formed over these regions. Usually, a chemical vapor deposition (CVD) technique is used to deposit the inter-level dielectric layer over the conductive regions. In a chemical vapor deposition process, chemicals containing the atoms or molecules required in the final film are mixed and reacted in a deposition chamber to form a vapor. The atoms or molecules deposit on the wafer surface and build up to form a film. Common CVD methods include atmosphere-pressure CVD (APCVD), low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD). The PECVD method provides an advantage over the APCVD and LPCVD methods in that it can be carried out at lower substrate temperatures. This is because the PECVD uses an rf-induced glow discharge or plasma to transfer energy into the reactant gases, rather than relying solely on thermal energy to initiate and sustain chemical reactions. This allows PECVD to be used to deposit films on substrates that do not have the thermal stability to accept coating by other methods, such as, for example, the formation of silicon nitride and silicon oxide over metals.
As advances are made in semiconductor technology, circuit elements and interconnections on wafers or silicon substrates are becoming more and more dense. As the circuit densities continue to increase, the widths of insulator-filled gaps or trenches, provided to physically and electrically isolate circuit elements and conductive lines, decrease. This increases the gap aspect ratio, which is usually defined as the gap height divided by the gap width. It is more difficult to fill these gaps with higher aspect ratios using the above CVD techniques, which can lead to unwanted voids and discontinuities in the insulating or gap-fill material.
Presently, high density plasma chemical vapor deposition (HDP-CVD) techniques are used to fill gaps having higher aspect ratios. HDP-CVD allows for the addition of a sputter component to the plasma deposition process which can be controlled to assist in gap-filling during deposition processes in a manner superior to the other CVD methods noted above. Typical HDP deposition processes employ chemical vapor deposition with a gas mixture containing oxygen, silane, and inert gases, such as argon, to achieve simultaneous dielectric etching and deposition. In an HDP process, an RF bias is applied to a wafer substrate in a reaction chamber. Some of these gas molecules, particularly argon, are ionized in the plasma and accelerate toward the wafer surface when the RF bias is applied to the substrate. Material is thereby sputtered when the ions strike the surface. This results in the dielectric material deposited on the wafer surface being simultaneously sputter etched. This helps to keep gaps open during the deposition process, which allows gaps with higher aspect ratios to be filled.
The conductive elements and interconnections, over which the interlevel dielectric is to be deposited, typically comprises a plurality of metal features, some of which have different sizes. A typical conductive pattern comprises a dense array of metal features, typically separated by gaps having a width of less than about one micron. However, a metal feature next to one of the metal features of the dense array, may be considerably larger than the metal features of the dense array. In the case where an adjacent feature has an upper surface area of a size greater than the upper surface area of the metal features of the dense array, then when a gap-filling dielectric layer is deposited, a step is formed with increasing height between the relatively smaller metal feature of the dense array and the relatively larger metal feature. With reference to
FIG. 1
, the metal features
15
and
17
of a dense array
12
have an upper surface area that is smaller than the upper surface area of a much larger metal feature
19
that is located next to the dense array
12
. When a dielectric layer
21
is deposited over the metal features
15
,
17
,
19
, a step
27
is formed between the thickness
23
of dielectric material required to cover the smaller features
15
,
17
and the thickness of dielectric material
25
required to cover the feature with the larger upper surface area. This step
27
makes it extremely difficult to planarize the dielectric layer that was deposited on the metal features. What is needed is a way to deposit a dielectric layer that minimizes the step height and improves the overall planarity of the layer across the semiconductor wafer.
It is the object of the present invention to provide a method of depositing an interlevel dielectric material on a semiconductor wafer that minimizes the amount of step height between metal features.
It is a further object of the present invention to provide a method of depositing an interlevel dielectric material on a semiconductor wafer based on a theoretical prediction of the high density plasma chemical vapor deposition thickness of the dielectric material that provides the best global planarity across the wafer and across each die.
SUMMARY OF THE INVENTION
The above objects have been achieved by a method of depositing an interlevel dielectric material on a semiconductor wafer at a selected thickness such that the best global planarity of the dielectric layer is achieved. A model for the deposition of a silicon dioxide dielectric layer is developed based upon the physics of deposition and sputtering, and based upon the minimum geometry of metal features in the semiconductor device. The HDP deposition model developed in this invention is then used to predict the optimum thickness of deposited film that, after a conformal cap deposition and chemical mechanical polishing (CMP) planarization, provides the best global planarity across the wafer. First, the geometric parameters of the metal features, such as the minimum width, pitch and height, are determined. Then, based upon the most aggressive aspect ratio between metal lines, the chemical vapor deposition rate to sputter rate ratio (D/S) is calculated. The optimum film thickness of the deposited oxide is determined based on the minimum width and space of the metal features, the height of the features, the deposition rate to sputter rate ratio, the angle of maximum sputter yield and the level of planarity required by the process. The dielectric material is then deposited on the metal features using HDP-CVD techniques in a manner using the calculated ratio to stop the deposition at the determined film thickness such that the optimum thickness for global planarity is achieved.
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Atmel Corporation
Lytle Craig P.
McGuire, Jr. John P.
Schneck Thomas
Smith Matthew
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