Method for depositing a flow fill layer on an integrated circuit

Details Method for depositing a flow fill layer on an integrated circuit Method for depositing a flow fill layer on an integrated circuit

1997-05-28

1999-04-06

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438632, 438760, 438902, 438787, H01L 21316

Patent

active

058918000

ABSTRACT:
An improved method for depositing a flow fill layer of an integrated circuit. Two flowlayers and two cap layers are deposited. The wafer is warmed between the deposition of the first cap layer and the deposition of the second flowlayer, to evaporate water from the first flowlayer. Preferably, each of the cap layers is deposited in two separate steps of plasma enhanced chemical vapor deposition, to inhibit crack formation in the flowlayers. Most preferably, after the depositions of each flowlayer, the flowlayer is planarized by flowing H.sub.2 O.sub.2 thereupon.

REFERENCES:
patent: 5003062 (1991-03-01), Yen
patent: 5079188 (1992-01-01), Kawai
patent: 5094984 (1992-03-01), Liu et al.
patent: 5192715 (1993-03-01), Sliwa et al.
patent: 5354387 (1994-10-01), Lee et al.
patent: 5364818 (1994-11-01), Ouellet
patent: 5395785 (1995-03-01), Nguyen et al.
patent: 5435888 (1995-07-01), Kalnitsky et al.
patent: 5503882 (1996-04-01), Dawson
patent: 5534731 (1996-07-01), Cheung
Kiermasz, A. Et al, "Planarisation for Sub-Micron Devices Utilising a New Chemistry", DUMIC Conference, pp. 94-100, Feb. 1995.
Matsuura, M. Et al, "Novel Self-planarizing CVD Oxide for Interlayer Dielectric Applications",IEEE IEDM, 1994, pp. 117-120.
Dobson, C.D. et al, "Advanced SiO.sub.2 Planarization Using Silane and H.sub.2 O.sub.2 ", Semiconductor Int'l., pp. 85-88, Dec. 94.
Roberts, B. et al, "Interconnect Metallization for Future Device Generations", Solid State Tech., pp. 69-70 (1995).
Wolf, S., "Silicon Processing for the VLSI Era", vol. 2, pp.194-196 (1990.
El-Kareh, B., "Fundamentals of Semiconductor Processing Technology", Kluwer Academic Pub., pp. 571-573 (1995).
Electotech Corp. Brochure, Thornbury Laboratories, Littleton-Upon-Severn, Bristol BS12 1NP, U.K. Tel: (0454) 419008.
Dobson et al, "Advanced SiO.sub.2 Planarization Using Silane and H.sub.2 O.sub.2 " Semiconductor Int'l., pp. 85-88, (Dec. 1994).
McClathe, et al, "Inorganic CVD Planarization", European Semiconductor, pp. 21-22, (Sep. 1995).

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