Method for defining alignment marks in a semiconductor wafer

Details Method for defining alignment marks in a semiconductor wafer Method for defining alignment marks in a semiconductor wafer

2005-06-07

2005-06-07

Deo, Duy-Vu N. (Department: 1765)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C257S797000

Reexamination Certificate

active

06902986

ABSTRACT:
A lithography and etching method for forming an alignment mark (104) and at least one device feature (such as a shallow trench105) on a wafer (99) is provided. The etching process (18) comprises: a first etching step (1811) for pre-defining at least one alignment mark (103) and a second etching step (1812) for defining desired semiconductor device patterns (such as a shallow trench105) on said wafer surface and completing said at least one alignment mark (104).

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patent: 6271602 (2001-08-01), Ackmann et al.
patent: 6673635 (2004-01-01), Hellig et al.
patent: 2002/0102811 (2002-08-01), Farrow et al.
Wolf et al., Silicon Processing for the VLSI Era, vol. 1, 1996, p. 427.

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