Abrading – Abrading process – Utilizing fluent abradant
Reexamination Certificate
1999-12-31
2003-07-15
Eley, Timothy V. (Department: 3724)
Abrading
Abrading process
Utilizing fluent abradant
C438S693000, C438S627000, C451S041000, C451S054000
Reexamination Certificate
active
06592433
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to removal of particles from a substrate and more particularly to removal of at least one particle from a metal layer deposited on a substrate using an acid.
2. Description of Related Art
Integrated circuits are made up of literally millions of active devices formed in or on a silicon substrate or well. The active devices that are initially isolated from one another are later connected together to form functional circuits and components. The devices are interconnected together through the use of well known multilevel interconnections. A cross-sectional illustration of a typical multilevel interconnection structure
10
is shown in FIG.
1
. Interconnection structures normally have a first layer of metallization, an interconnection layer
12
(typically aluminum alloys with up to 3% copper), a second level of metallization
14
, and sometimes a third or even fourth level of metallization. Interlevel dielectrics
16
(ILDs), such as doped and undoped silicon dioxide (SiO
2
), are used to electrically isolate the different levels of metallization in silicon substrate or well
18
. The electrical connections between different interconnection levels are made through the use of metallized vias
11
formed in ILD
16
. In a similar manner, metal contacts
22
are used -to form electrical connections between interconnection levels and devices formed in well
18
. The metal vias
11
and contacts
22
, hereinafter being collectively referred to as “vias” or “plugs”, are generally filled with tungsten
14
and generally employ an adhesion layer
16
such as TiN. Adhesion layer
16
acts as an adhesion layer for the tungsten metal layer
14
which is known to adhere poorly to SiO
2
. At the contact level, the adhesion layer acts as a diffusion barrier to prevent W and Si from reacting.
In one process, metallized vias or contacts are formed by a blanket tungsten deposition and a chemical mechanical polish (CMP) process. In a typical process, via holes
23
are etched through an ILD
24
to interconnection lines or a semiconductor substrate
26
formed below. Next, a thin adhesion layer
28
, such as TiN, is generally formed over ILD
24
and into via hole
23
, as shown in
FIG. 2
b
. Next, a conformal tungsten film
29
is blanket deposited over the adhesion layer and into the via hole
23
. The deposition is continued until the via hole
23
is completely filled with tungsten. Next, the metal films formed on the top surface of ILD
24
are removed by CMP, thereby forming metal vias or plugs
28
.
In a typical CMP process as shown in
FIG. 2
c
, the substrate or wafer
30
is placed face-down on a polishing pad
32
which is fixedly attached to a rotatable platen
34
. In this way, the thin film of a metal layer to be polished (i.e., tungsten film
29
) is placed in direct contact with pad
32
. A carrier
36
is used to apply a downward pressure F
1
against the backside of substrate
30
. During the polishing process, pad
32
and platen
34
are rotated while a downward force is placed on substrate
30
by carrier
36
. An abrasive and chemically reactive solution, commonly referred to as “slurry”
35
is introduced onto pad
32
during polishing. Slurries generally include an abrasive material such as alumina or silica. The slurry initiates the polishing process by chemically reacting with the film being polished. The polishing process is facilitated by the rotational movement of pad
32
relative to wafer
30
as slurry is provided to the wafer/pad interface. Polishing is continued in this manner until all of the film on the insulator is removed.
After the polishing process, the substrate is then rinsed with a solution such as deionized water. By rinsing the substrate, particles from the slurry are removed from the metallized layer.
Conventional rinsing methods include using a double sided scrubber using deionized water for removing particles present from the CMP from a metallized layer. However, using deionized water generally does not remove all of the particles. Another conventional method is a “magasonic” bath which involves high frequency vibration in which particles are shaken off the substrate. This method also leaves particles on the metal layer.
Removing foreign particles from a substrate that is used in integrated circuits is known in the art. One known method involves introducing a slurry over a substrate and polishing the substrate. The substrate is then rinsed with deionized water. A scrubber then cleans the substrate. However, this method is problematic because it is unable to remove the particles to a nondetectable level.
FIG. 8
shows that a substrate using a conventional method such as that which is described above leaves a large quantity of defects on the substrate. Particles on a substrate may affect the electrical conductivity between the various layers of the interconnect within an integrated circuit and cause catastrophic failures upon further processing. Accordingly, it is desirable to have a method and an apparatus wherein particles are removed from a substrate to a nondetectable level of particles without affecting adhesion or the integrity of the post-polish metal layer surface.
SUMMARY OF THE INVENTION
A metal layer is cleaned by introducing an acid onto the metal layer.
REFERENCES:
patent: 3879216 (1975-04-01), Austin
patent: 4541945 (1985-09-01), Anderson et al.
patent: 4755230 (1988-07-01), Ashton et al.
patent: 5633068 (1997-05-01), Ryoke et al.
patent: 5639722 (1997-06-01), Kong et al.
patent: 5709588 (1998-01-01), Muroyama
patent: 5817569 (1998-10-01), Brenner et al.
patent: 5896875 (1999-04-01), Yoneda
patent: 5972124 (1999-10-01), Sethuraman et al.
patent: 6022400 (2000-02-01), Izumi et al.
patent: 6169034 (2001-01-01), Avanzino et al.
patent: 6178585 (2001-01-01), Cadien et al.
patent: 6190237 (2001-02-01), Huynh et al.
patent: 6217416 (2001-04-01), Kaufman et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Eley Timothy V.
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