Method for decreasing time penalty resulting from a cache miss i

Details Method for decreasing time penalty resulting from a cache miss i Method for decreasing time penalty resulting from a cache miss i

1994-02-14

1997-02-11

Harvey, Jack B.

395449, 395471, 395460, 395450, G06F 1200, G06F 1212

Patent

active

056030045

ABSTRACT:
A cache system buffers data stored in a main memory and utilized by a processor. The cache system includes a first cache, a second cache, a first transfer channel, a second transfer channel and a third transfer channel. The first cache is fully associative. The second cache is directly mapped. The first transfer channel transfers data lines from the main memory to the first cache. The second transfer channel transfers data lines from the first cache to the second cache. The third transfer channel transfers data lines from the second cache to the main memory. Accesses of data lines from the first cache and the second cache are performed in parallel.

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Norman P. Jouppi, Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, Proceedings 17th ISCA, May 1990, pp. 364-373, Seattle, WA.

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