Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-12-09
2001-08-21
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S624000, C438S631000, C438S669000, C438S637000, C438S625000, C257S758000, C156S922000
Reexamination Certificate
active
06277726
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of fabricating an integrated circuit and more specifically to a method for reducing the resistance of electrical coupling between conductive layers in vias or contact holes.
2. Background of the Invention
Several factors adversely impact the effectiveness of multilevel interconnects. Among them include, but are not limited to, misalignment of vias or contact holes caused by the via patterning process and the failure to remove resistive compounds formed on electrodes positioned in the misaligned contact holes. These two factors cause an increase in resistance of the contact holes, resulting in poor conduction between the levels of the interconnect. Consequently, the reliability of the produced device is diminished. As VLSI feature sizes continues to shrink, for example to sub 0.25 &mgr;m region, the problem of misaligned or “unlanded” vias seem unavoidable. Thus, to improve device performance and reliability, as related to conduction between conductive layers, it would be desirable to reduce or eliminate the presence of the aforementioned resistive compounds.
To pose the problem more concretely by way of example, aluminum (Al) is a preferred material for electrodes because it is lightweight, corrosion resistant, and inexpensive. However, aluminum is porous and has a high effective surface area capable of easily adsorbing oxygen and water vapor. As a result, during the processing of multilevel interconnects, a native oxide layer is formed on the aluminum. The oxidized aluminum acts as a resistive film.
As discussed above, the problem of conductivity is also heightened due to the misalignment of vias or contact holes. Ideally, as illustrated in
FIG. 1
, the vias
2
should be positioned directly above the aluminum electrodes
4
, as depicted by area X. Referring to
FIG. 1
, there is illustrated a substrate
6
supporting the electrodes
4
. An intermediate dielectric layer
8
separates the electrodes
4
from a second level of interconnect
10
. The direct alignment of tungsten (W) filled vias
2
on the aluminum electrodes
4
can provide a resistance of about 1 &OHgr; to about 2 &OHgr; for the contact holes
2
. When the tungsten filled vias
2
are misaligned or “unlanded,” generally illustrated by area Y in
FIG. 2
, the resistance of the contact holes can increase, causing the reliability of the device to suffer.
The combination of having an oxidized aluminum electrodes
4
and misaligned tungsten filled vias
2
, therefore, can produce a resistance about 8-10 &OHgr;, for the contact holes
2
. This combination is illustrated in FIG.
2
. In order to compensate for the increase in resistivity caused by the misalignment of the contact holes
2
, the resistance of the aluminum electrode
4
has to be decreased. Therefore, the active conductive contact area (i.e., the area not covered by native oxide) of the aluminum electrode
4
must be enlarged. The only active contact area of aluminum electrode
4
is area D, an area which is typically covered by titanium nitride
5
. It is desirable to remove the oxidized aluminum film, as illustrated by shaded area
7
, from the aluminum electrode
4
, and in effect, to make contact area C active. The activation of contact area C produces a resistivity of about 2 &OHgr; to about 3 &OHgr; for the “unlanded” tungsten filled contact holes
2
, a decline of about 5 &OHgr; to about 8 &OHgr;.
SUMMARY OF THE INVENTION
The present invention accomplishes its desired objects by broadly providing a method for decreasing contact resistance of an electrode, comprising:
a) providing an electrode having a resistive film formed thereon;
b) removing the resistive film from the electrode; and
c) forming a protective layer on the electrode.
The electrode can comprise an aluminum layer supported by a titanium nitride layer or a titanium/titanium nitride bi-layer. The resistive film may comprise native oxide, formed on the electrode during etching or processing of the electrode. The removing step (b) comprises employing a plasma of an etchant gas to etch and remove the resistive film from the electrode. The etchant gas includes about 100% by volume argon.
After the resistive film has been removed from the electrode, a protective layer is formed on the electrode. Preferably, the protective layer comprises titanium nitride. Alternatively, the protective layer may comprise a titanium/titanium nitride stack.
The present invention also accomplishes its desired objects by broadly providing a method for manufacturing a multilevel interconnect, comprising:
a) providing a first electrode layer on a substrate;
b) removing a portion of the first electrode layer from the substrate to produce metal lines, the metal lines having a resistive film formed thereon during processing of the metal lines;
c) etching the metal lines of step (b) including employing a plasma of an etchant gas to remove the resistive film;
d) forming a protective layer on the substrate and the metal lines, the protective layer having intermediate portions;
e) etching the intermediate portions of the protective layer to break through and remove the intermediate portion from the substrate;
f) forming a dielectric layer on the substrate and the metal lines;
g) etching vias in the dielectric layer to expose a portion of the metal lines;
h) filling the vias with plugs; and
i) forming a second electrode layer on the dielectric layer and the plugs to produce a multilevel interconnect.
The first electrode layer, as discussed above, comprises a titanium nitride layer supporting an aluminum layer. The first electrode layer may additionally comprise a titanium layer disposed under the titanium nitride layer. The first electrode layer may additionally comprise a second titanium nitride layer disposed on the aluminum layer. Selected portions of the first electrode layer is etched or removed from the substrate to form metal lines. During the processing of the metal lines, a resistive film, such as native oxide, is formed on the metal lines. In other words, a portion of the aluminum is oxidized. As stated previously, the resistive film is etched from the metal lines by employing a plasma of an etchant gas comprising about 100% by volume argon.
As discussed previously, after the resistive film has been removed from the metal lines, a protective layer is formed on the metal lines, including the substrate. The protective layer that is formed on an intermediate portion, i.e., the space between the metal lines, is etched and removed from the substrate. The protective layer that is formed on top of the metal lines is also removed. In the alternative embodiment, the protective layer that is formed on the second titanium nitride layer on top of the metal lines is removed.
A first level of the multilevel interconnect is now in condition for the addition of the next level. A dielectric layer is formed on the substrate and the metal lines. The dielectric layer may, for example, comprise silicon or a fluorine based compound having a low dielectric constant. Contact holes or vias are patterned in the dielectric layer to expose a portion of the metal lines. A film comprising, for example, titanium/titanium nitride, is formed on the dielectric layer. Additionally, the film is formed on inside surfaces of the contact holes. The contact holes are filled with plugs, such as tungsten. A second electrode layer may be disposed on the dielectric layer and the plugs, thus creating a multilevel interconnect.
REFERENCES:
patent: 4917759 (1990-04-01), Fisher et al.
patent: 5420078 (1995-05-01), Sikora
patent: 5534462 (1996-07-01), Fiordalice et al.
patent: 5656543 (1997-08-01), Chung
patent: 5656861 (1997-08-01), Godinho et al.
patent: 5702981 (1997-12-01), Maniar et al.
patent: 5798299 (1998-08-01), Chung
patent: 5801093 (1998-09-01), Lin
S. Wolf, Silicon Processing for the VLSI Era, vol. 1, Process Technology, Mar. 1986.
Kitch Vassili
Thomas Michael E.
Keshavan Belur
Kwok Edward C.
National Semiconductor Corporation
Skjerven Morrill & MacPherson LLP
Smith Matthew
LandOfFree
Method for decreasing contact resistance of an electrode... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for decreasing contact resistance of an electrode..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for decreasing contact resistance of an electrode... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2519351