Electrical computers and digital processing systems: memory – Address formation – Address multiplexing or address bus manipulation
Reexamination Certificate
1998-07-07
2002-02-19
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address multiplexing or address bus manipulation
C711S209000, C365S230060, C365S233100
Reexamination Certificate
active
06349376
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to address decoding. More particularly, the present invention relates to enhancing the speed and efficiency of address decode operations. Specifically, the present invention relates to enhancing the speed and efficiency of address decode operations that consume more than one clock cycle.
BACKGROUND OF THE INVENTION
In a computer system, a device may initiate an address request to, for example, write to or read from an addressable address range of another device. To process these address requests, the computer system has address decoding logic to decode the addresses and determine the destination of the address requests. In a typical computer system, these address decode operations may be performed by comparing the address to be decoded with the addressable address ranges within the computer system. When the address decoding logic determines that the address to be decoded is within a certain address range, the destination specified by the address request and other information relating to the address request is known or may be determined. The destination and other information (hereinafter referred to as the “results of an address decode operation”) may be provided to routing logic for routing to the specific address range requested.
In order to minimize the number of “compares” required to decode an address (and, therefore, the number of clock cycles required to decode an address), the address to be decoded may be compared to address ranges that are addressed relatively more frequently before being compared to address ranges that are addressed relatively less frequently. For example, the address to be decoded may be compared to the most frequently addressed address ranges in the computer system during a first clock cycle. If the address to be decoded does not fall within these address ranges, the address to be decoded may be compared to address ranges that are addressed relatively less frequently during a second clock cycle. This comparison process may continue for more than 2 clock cycles until an address range “match” is found.
As computer systems become larger, the efficiency and speed of address decode operations may decrease. In relatively larger computer systems, the number of addressable address ranges may be increased. Accordingly, in relatively larger computer systems, there may be a relatively greater number of “multi-clock addresses” or addresses that cannot be decoded in a single clock cycle. In general, as the number of multi-clock addresses increases, the number of “multi-clock address decode operations” increases. An increase in the number of multi-clock address decode operations decreases a computer system's speed, efficiency and throughput.
Relatively large numbers of multi-clock addresses may be a particular problem during “bursting” operations or operations in which a particular address range is the subject of repeated, uninterrupted address requests from an address request initiating device. If the address range requested in a bursting operation is a multi-clock address, the address decode operation will repeatedly consume 2 or more clock cycles to decode the multi-clock address while the bursting operation is continued.
Thus, there exists a need in the art for apparatus and methods for decreasing the amount of multi-clock address decode operations in a computer system comprising multi-clock addresses.
SUMMARY OF THE INVENTION
One embodiment of the present invention comprises a method for providing the results of an address decode operation comprising comparing the address to be decoded with the address range of an address previously decoded in a previous address decode operation, selecting the results of the previous address decode operation if the address to be decoded is within the address range of the address decoded in an previous address decode operation, and decoding the address to be decoded in a current address decode operation and selecting the results of the current address decode operation if the address of the address to be decoded is not within the address range of an address previously decoded in a previous address decode operation.
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patent: 5805523 (1998-09-01), Lysinger
patent: 5860113 (1999-01-01), Tung
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Micron 1996 DRAM Data Book, pp. 3-1 and 3-2, Dec. 1995.
Portka Gary J.
Yoo Do Hyun
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