Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-04-14
2002-01-01
Le, Dieu-Minh (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S056000, C710S065000
Reexamination Certificate
active
06336195
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for debugging a computing system, more particularly to a method for debugging keyboard basic input/output system (KB-BIOS) in a development notebook computing system.
2. Description of the Related Art
The architecture of a conventional computing system can be generally defined using functional layers. The lowest functional layer is the actual machine or hardware, whereas the highest functional layer is the application program for interfacing with the user. Between the hardware and the application program, there is provided the system software that is composed of several elements, including the operating system kernel and shell, the device drivers, and in some instances, the multitasking supervisor.
Conventional computing systems further include a system basic input/output system (SYS-BIOS) between the hardware and the system software. Notebook computing systems additionally include a keyboard basic input/output system (KB-BIOS) between some of the hardware and the SYS-BIOS. Referring to
FIG. 1
, in a notebook computing system, the hardware associated with SYS-BIOS
10
include the floppy disk drive (FDD), the hard disk drive (HDD), the CD-ROM drive (CDROM), the PCMCIA port, the computer monitor (CRT), and the computer printer (LPT). On the other hand, the hardware associated with KB-BIOS
11
include the battery pack, the EEPROM, the thermal sensor, the internal keyboard (INT-KBD), and auxiliary ports (AUX
1
, AUX
2
) for the external keyboard (EXT-KBD) and the external PS/2 mouse. KB-BIOS
11
communicates with SYS-BIOS
10
via the ISA bus. KB-BIOS
11
insulates SYS-BIOS
10
from the hardware that is associated therewith, such as the internal keyboard and the PS/2 mouse, by providing basic I/O services and by processing interrupt signals that are generated by the hardware.
Most computing systems are mainly controlled through the use of interrupts, which can be generated by the microprocessor, by the system hardware, or by the software itself. KB-BIOS can provide a logical handling of the interrupt signals. When an interrupt occurs, processor control is transferred to an interrupt vector. The interrupt vector stores an address assigned by KB-BIOS. Routing to the correct service routine for execution subsequently occurs according to the stored address.
KB-BIOS Interrupt Service Routines (ISRs) handle interrupts issued by hardware devices. ISRs use registers in the processor, the memory (RAM) and the KB-BIOS data area. KB-BIOS also uses various GPIO ports.
It is known that debugging of BIOS in a computing system can be conveniently performed with the use of an in-circuit emulator (ICE). An ICE physically replaces the processor in a target or development machine. A host computer is connected to the ICE via a buffer. The ICE is connected to the development machine through another buffer. BIOS commands are received by the ICE through the buffers, and are processed using routines resident in a RAM of the ICE. As such, the BIOS of the development machine can accurately access the data in the RAM of the ICE.
ICE technology has many drawbacks. For example, ICE software can only run in expensive specially designed machines or processing equipment. An ICE tester requires removal of the microprocessor on the development machine, and a socket on the development machine for connection with the ICE tester. In addition, whenever a new microprocessor enters the market, ICE testing of a development machine using the new microprocessor is not possible unless system specific ICE software has already been developed therefor.
Software debugging programs, such as Soft-ICE, allow for analysis of BIOS commands issued by application programs. However, these systems require fully functional hardware, microprocessor, memory, stacker, BIOS and operating system on the development machine. Thus, only BIOS commands associated with the application program can be analyzed.
Conventional KB-BIOS debugging in a development notebook computing system is a fairly complicated task that involves sending of debug data to SYS-BIOS via port
60
/
64
or port
62
/
66
of the ISA bus for showing the debug data on the computer monitor (see FIG.
1
). Therefore, conventional KB-BIOS debugging is not possible without the assistance of SYS-BIOS.
U.S. Pat. No. 5,615,331 discloses a BIOS-level real-time debugger for a development computing system. The debugger is resident in the development computing system and does not require external hardware circuitry for the debugging interface. In the aforesaid patent, it was not specified that the development computing system is a notebook computing system, and no distinction was made between SYS-BIOS and KB-BIOS. Thus, no disclosure was made regarding the debugging of KB-BIOS without the assistance of SYS-BIOS.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a low-cost, relatively simple, KB-BIOS-level real-time debugging method for a development notebook computing system. The method dispenses with external hardware circuitry for the debugging interface, and involves communicating of debugging information to a remote host computer via a serial PS/2 port without assistance from SYS-BIOS of the development notebook computing system.
According to the present invention, there is provided a computer-implemented method for debugging KB-BIOS in a development notebook computing system. The KB-BIOS includes a KB-BIOS processor and a memory that is coupled to the KB-BIOS processor and that has a resident debug engine module. The development notebook computing system further has a SYS-BIOS that is separate from the KB-BIOS and that communicates with the KB-BIOS via an ISA bus. The method comprises the steps of:
coupling a serial PS/2 port, that is connected to the KB-BIOS processor and that serves as a communications channel, of the development notebook computing system to a host computer so as to establish communication between the KB-BIOS and the host computer;
sending a debug command from the host computer to the development notebook computing system via the serial PS/2 port; and
at the development notebook computing system, directing the debug command sent by the host computer via the serial PS/2 port and without passing through the ISA bus to the KB-BIOS processor so as to enable the KB-BIOS processor to execute the debug command according to program instructions in the debug engine module and to send debug data associated with the development notebook computing system to the host computer via the serial PS/2 port and without passing through the ISA bus in response to execution of the debug command.
As such, KB-BIOS debugging of the development notebook computing system can proceed without assistance from the SYS-BIOS.
Preferably, the debug data is written in a queue buffer in the KB-BIOS processor before sending the debug data to the host computer via the serial PS/2 port in order to increase debug data transmission speed to the host computer.
REFERENCES:
patent: 5615331 (1997-03-01), Toorians et al.
patent: 5892943 (1999-04-01), Rockford et al.
patent: 6065081 (2000-05-01), Stancil et al.
patent: 6142683 (2000-11-01), Madduri
patent: 6175914 (2001-01-01), Mann
patent: 6189140 (2001-02-01), Madduri
Lin Tzu-Wen
Shen Yi-Hung
Compal Electronics Inc.
Le Dieu-Minh
Pillsbury & Winthrop LLP
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