Patent
1995-06-05
1998-10-13
An, Meng-Ai T.
395445, 395481, 395872, 395859, G06F 1338, G06F 1314
Patent
active
058226117
ABSTRACT:
A method of arranging and operating a cache in a multi-processor computer system with N local processors, where a requesting device can request a cycle to be issued, where the method involves "posting" the "cycles", while also storing information for completing a cycle in a Queue and causing the requesting device to be issued "termination" immediately, rather than waiting for the cycle to reach its destination.
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Donley Greggory D.
Gujral Manoj
Israel Paul N.
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