Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-01-18
2004-04-27
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S166000, C438S486000, C438S487000, C438S795000
Reexamination Certificate
active
06727121
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a thin film transistor (TFT) that is used in liquid crystal display (LCD), organic light emitting diode (OLED) and 3-D integrated semiconductor device or the like, and more particularly to a method for crystallizing an active layer forming the source, drain and channel regions of a thin film transistor using crystal filtering technique.
BACKGROUND OF THE INVENTION
According to the present invention, the active layer of a thin film transistor can be crystallized into single crystalline silicon by filtering a crystal component having a uniform crystal orientation from a poly-crystal region which is crystallized by metal induced lateral crystallization (MILC) caused by MIC source metal.
Generally, the amorphous silicon transistor used in display devices such as LCD and OLED is fabricated by forming a gate electrode on a transparent substrate of glass or quartz, depositing gate oxide film, depositing amorphous silicon and n-type amorphous silicon, forming source and drain regions, and then forming an insulating layer. Generally, the active layer constituting the source, drain and channel regions of a thin film transistor is formed on a substrate such as glass or quartz using chemical vapor deposition (CVD) method. Since the active layer formed by CVD is made of amorphous silicon, it has low electron mobility of 1 cm
2
/Vs or less. As the size of LCD using TFT is being miniaturized and its aperture ratio is being reduced, a technique that may simultaneously form the drive IC and the pixel transistor has been required. In order to do so, a technique of crystallizing an amorphous silicon layer into a poly-crystal silicon layer with thermal treatment is used.
A poly-crystal silicon layer transistor is formed by first depositing an amorphous silicon layer on a substrate of glass or quartz and the like, poly-crystallizing the silicon layer and forming a gate oxide film and a gate electrode, implanting dopant in the source and drain, activating the dopant through annealing, and finally forming an insulating layer. Generally, the electron mobility of poly-crystal silicon layer is in the range of ~100 cm
2
/Vs. Thus, using the poly-crystal silicon, the drive IC of LCD may be integrated into the same substrate with the pixel transistors. The important factors that determine the characteristics of a poly-crystal TFT are the number and configuration of the crystal grains boundaries existing in the poly-crystal silicon. According to the number and configuration of the grain crystal boundaries in the poly-crystal silicon, the electron mobility and the threshold voltage of the poly-crystal thin film transistor vary significantly.
As a poly-crystal thin film transistor inevitably includes crystal grain boundaries in its active layer made of poly-crystal silicon, it has lower electron mobility as compared to the electron mobility of 800 cm
2
/Vs of single crystalline silicon and higher degree of device non-uniformity. When fabricating a LCD using poly-crystal silicon layer transistors, the drive IC and the pixel transistor may be formed on the same substrate. However, due to the electron mobility of the poly-crystal silicon which is much lower than that of single crystal silicon, active elements such as the LCD controller, DAC, clock generator or the like may not be formed on the substrate. Also the increased device non-uniformity causes the deterioration of the display quality and the decreases of the productivity. Therefore, in order to secure uniform device characteristics equivalent to a single crystalline silicon device, some techniques for forming a single crystalline silicon layer with an amorphous silicon layer have been used.
A variety of methods for fabricating single crystalline silicon transistor have been proposed. Sequential lateral solidification (SLS) is a technique that forms single crystalline silicon in a local region while crystallizing an amorphous silicon layer by laser scanning using Chevron-type masks. The SLS method has a technical problem in precisely controlling the scanning of the laser beam. The method also has a limitation in obtaining single crystalline thin film having uniform characteristics because the crystal grains in the poly-crystal silicon frequently infiltrates into the locally formed single crystal silicon region. Also, as this method may process only one substrate at a time, the productivity of the process is lower than that of the batch process using a furnace.
Continuous grain solidification (CGS) is a technique that obtains crystallized silicon layer having substantially uniform crystal orientation by contacting or implanting metal such as nickel, palladium, aluminum and the like in amorphous silicon and crystallizing the amorphous silicon at a low temperature of 200~500° C. The CGS method has a disadvantage of requiring a gettering process, which involves an additional thermal treatment to remove the silicide component used as a catalyst for crystallizing the amorphous silicon. And, as the silicon layer formed by the CGS method is not essentially single crystalline, its electrical characteristics are inferior to those of a single crystal silicon film.
Recently, a method for crystallizing a silicon layer by using metal induced lateral crystallization (MILC) phenomenon was proposed. (See S. W. Lee et al.,
IEEE Electron Device Letter,
17(4), p.160, 1996) The MILC phenomenon induces successive crystallization of amorphous silicon layer as the silicide produced by the reaction of the metal and the amorphous silicon propagates in the lateral direction of the silicon layer. When the MILC method is used, as the metal component used to crystallize the amorphous silicon does not remain in the crystallized region, it avoids the problem that the metal component remaining in the crystallized silicon region causes leakage current and deteriorates other electrical characteristics. Also, when using the MILC method, as the crystallization of silicon layer is induced at relatively low temperature of 300~500° C., a plurality of substrates may be simultaneously crystallized in a furnace without causing damages to the substrates.
FIG. 1
a
to
FIG. 1
d
are cross-sectional views illustrating the process of prior art for crystallizing a silicon layer constituting the active layer of a thin film transistor using MIC and MILC.
Referring to
FIG. 1
a
, an amorphous silicon layer
10
is deposited on an insulating substrate
100
on which a buffer layer (not illustrated) is formed. Then the amorphous silicon layer
10
is patterned to form an active layer. A gate insulating layer
11
and a gate electrode
12
are formed on the active layer using conventional methods. As shown in
FIG. 1
b
, a source region
10
S and a drain region
10
D are respectively formed in the active layer by doping impurity into the whole substrate using the gate electrode as a mask. As shown in
FIG. 1
c
, photoresist
13
is formed to cover the gate electrode and the source and drain regions adjacent the gate electrode
12
and then a metal layer
14
is deposited on the entire surface of the photoresist
13
and the substrate. It is desirable that the metal layer is formed by depositing Ni at a thickness of about 20. As shown in
FIG. 1
d
, when performing thermal treatment of the entire substrate at temperature of 300° C. to 500° C. after removing the photoresist, the source and drain regions below the metal layer remaining after the removal of the photoresist is crystallized by metal induced crystallization (MIC) that directly crystallizes the silicon by the MIC source metal which is in contact with or implanted in the amorphous silicon. And the amorphous silicon in the metal offset region and in the channel region
10
C beneath the gate electrode is crystallized by the MILC that propagates from the MIC region. As shown in
FIG. 1
a
to
FIG. 1
d
, the photoresist is formed to cover portions of the source and the drain regions on both sides of the gate electrode
12
. It is because, if the metal layer
14
is deposited up to boundaries between th
Joo Seung Ki
Lee Seok-Woon
Baker & Botts L.L.P.
Koo Seung Ji
Trinh Michael
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