Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-04-04
2006-04-04
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07024638
ABSTRACT:
To increase the writing speed of masks, context information can be used to distinguish the attributes of portions of the mask that are critical from attributes, and portions, that are less critical. By using this information, which may be derived from the design context of the features, the mask can be written at a higher speed without sacrificing the accuracy of the important attributes or features.
REFERENCES:
patent: 5553273 (1996-09-01), Liebmann
patent: 5553274 (1996-09-01), Liebmann
patent: 5567550 (1996-10-01), Smayling
patent: 5580687 (1996-12-01), Leedy
patent: 5740068 (1998-04-01), Liebmann et al.
patent: 5821014 (1998-10-01), Chen et al.
patent: 5879868 (1999-03-01), Starikoy et al.
patent: 5932377 (1999-08-01), Ferguson et al.
patent: 6051347 (2000-04-01), Tzu et al.
patent: 6168891 (2001-01-01), Shibata
patent: 6282696 (2001-08-01), Garza et al.
patent: 6285488 (2001-09-01), Sandstrom
patent: 6421820 (2002-07-01), Mansfield et al.
patent: 6456899 (2002-09-01), Gleason et al.
patent: 6529621 (2003-03-01), Glasser et al.
patent: 6535774 (2003-03-01), Bode et al.
patent: 6560766 (2003-05-01), Pierrat et al.
patent: 6571383 (2003-05-01), Butt et al.
patent: 6578188 (2003-06-01), Pang et al.
patent: 6579651 (2003-06-01), Subramanian et al.
patent: 6634018 (2003-10-01), Randall et al.
patent: 6658640 (2003-12-01), Weed
patent: 6670082 (2003-12-01), Liu et al.
patent: 6703167 (2004-03-01), LaCour
patent: 6787271 (2004-09-01), Cote et al.
patent: 2002/0026626 (2002-02-01), Randall et al.
patent: 2002/0102476 (2002-08-01), Hayano et al.
patent: 2002/0155357 (2002-10-01), LaCour
patent: 2002/0157068 (2002-10-01), LaCour et al.
patent: 2002/0160281 (2002-10-01), Subramanian et al.
patent: 2003/0018948 (2003-01-01), Chang et al.
patent: 2003/0023939 (2003-01-01), Pierrat et al.
patent: 2003/0160980 (2003-08-01), Olsson et al.
patent: 2003/0165749 (2003-09-01), Fritze et al.
patent: 2003/0200523 (2003-10-01), Takahashi et al.
patent: 2004/0013952 (2004-01-01), Elian et al.
patent: 2004/0044984 (2004-03-01), Keogan et al.
patent: 2004/0067423 (2004-04-01), Chen et al.
patent: 2004/0107412 (2004-06-01), Pack et al.
patent: 2004/0133369 (2004-07-01), Pack et al.
patent: 2004/0172610 (2004-09-01), Liebmann et al.
Liebmann, LW. et al., “TCAD Development for Lithography Resolution Enhancement”, IBM Journal of Research and Development, vol. 45, No. 5, Sep. 2001.
Wong, Alfred K., “Resolution Enhancement Techniques in Optical Lithography”, SPIE Press, 2001, Chapter 1.
Goering, R. “SEMI's Oasis provides respite from GDSII”,EE TimesOct. 1, 2002.
Pack, R.C. et al., “GDS-3 Initiative: Advanced Design-through-Chip Infrastructure for Sub-Wavelength Technology”, Proceedings of SPIE, vol. 4692, 2002, pp. 566-584.
Abe Yoshikuni
Fujimura Aki
Pack Robert C.
Scheffer Louis K.
Yoshida Kenji
Bingham & McCutchen LLP
Cadence Design Systems Inc.
Levin Naum
Smith Matthew
LandOfFree
Method for creating patterns for producing integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for creating patterns for producing integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for creating patterns for producing integrated circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3591470