Method for creating a design verification test bench

Details Method for creating a design verification test bench Method for creating a design verification test bench

2000-12-18

2002-12-03

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06490711

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to digital design verification, and more specifically to a method for creating a design verification test bench using automatic test pattern generation (“ATPG”) and test strategies based on circuit-type classifications.
BACKGROUND OF THE INVENTION
Test benches for very large scale integrated circuit (“VLSI”) designs are difficult and time consuming to create. Additionally, the complexity of circuits is not being fully explored during (non-formal) verification testing. The techniques now being used to create test benches rely on an application of human intuition in the form of waveform editing and test benches written in a hardware description language (“HDL”), such as Verilog and VHDL.
These intuitive approaches suffer from the limitations that once plagued manufacturing test generation—the complexity overwhelms most human designers. Testing based on intuition is therefore generally inadequate, is prone to human design error, and takes much too long to create. The efforts of electronic design automation (“EDA”) tool designers have been directed primarily at helping the designer to produce larger designs in reasonably short time frames. Only a limited effort has been directed at helping the designer or test bench creator to create more useful test benches in less time. As a result, there is currently an imbalance between what a designer can produce and the ability of anyone to create test benches to adequately verify the design. What are needed are more powerful tools to aid in the creation of test benches.
The current state of the art is to provide rather elaborate assistance with waveform editing and HDL creation of test benches, but few tool makers have presented tools that help the test bench creator produce complex tests automatically, rapidly, in volume, and relatively free of error. The graphical means featured by many of today's top-flight EDA tools are simply inadequate to the needs of serious designers of large digital circuits. Waveform editing, no matter how user friendly, cannot produce the volume and quality of tests needed for large circuits. Forcing designers to work with these graphical tools—or, alternatively, requiring the designer to create test stimuli and expected responses using HDL techniques—slows the entire design process. Also, the graphical techniques rely entirely on human intuition to create test stimuli and expected responses.
SUMMARY OF THE INVENTION
The present invention offers a solution to this dilemma. The invention is a test bench creation tool (
FIG. 1
) that is to be integrated into typical EDA design tool suites, preferably as part of a simulation package. The tool provides a designer with an ability to classify parts of a design using such techniques as special comment lines. Once the parts of a design have been classified in this manner, the tool (or alternatively, the designer) selects pre-existing test bench HDL design templates suitable for the identified circuit classes. These HDL design templates provide much of the boilerplate programming that must exist in any test bench effort. The templates require the tool (or alternatively, the designer) to provide circuit parameters such as bus width, etc. ATPG techniques are available for invocation by the designer to develop tests for combinational logic, and test sequences for sequential logic according to the circuit classifications. The ATPG techniques also create expected responses for use in comparison with actual responses. The tool (or alternatively, the designer) copies the test stimuli and expected responses into the test bench templates to complete the test bench. The completed test benches are applied to the circuits being tested via a simulation tool (FIG.
2
).
The ATPG techniques used in manufacturing test are not directly suitable for verification testing and must be modified somewhat to provide useful test bench stimuli. The goal in verification is to demonstrate that the HDL defines a circuit that does what the designer intended it to do, rather than to prove that the HDL does what a fault-free copy of the circuit does—the latter process sometimes called validation.
The test bench should operate in two modes, (1) a functional verification mode in which a few simple tests are applied to give the designer some assurances that the overall structure operates as intended, without too much attention to detail. A second mode (2) applies detailed tests and expected results to prove that there are no hidden surprises in the design.
Waveforms are useful during the functional verification mode because they rapidly give a designer confidence that the circuit is working properly—it is important to remember that the goal here is to bring a very large design up to speed as rapidly as possible.
During the detailed mode of operation, waveform inspection is used only when a designer wants to zero in on a specific area, or when comparison with expected results fails.
There is a fundamental problem here that the present invention does not address: the expected results are derived from an analysis of the HDL, so if there is some subtle error in the HDL it won't be caught by test benches produced in this way. That shortcoming notwithstanding, the present invention is an improvement over much of what is being offered today.


REFERENCES:
patent: 5812416 (1998-09-01), Gupte et al.
patent: 5903475 (1999-05-01), Gupte et al.
patent: 5923867 (1999-07-01), Hand
patent: 5953519 (1999-09-01), Fura
patent: 5963454 (1999-10-01), Dockser et al.
patent: 6026226 (2000-02-01), Heile et al.
patent: 6076180 (2000-06-01), Meyer
patent: 6077304 (2000-06-01), Kasuya
patent: 6083269 (2000-07-01), Graef et al.
patent: 6128025 (2000-10-01), Bright et al.
patent: 6141630 (2000-10-01), McNamara et al.
patent: 6161211 (2000-12-01), Southgate
patent: 6263483 (2001-07-01), Dupenloup
patent: 6289498 (2001-09-01), Dupenloup
P.C. Ward et al., Behavioral Fault Simulation in VHDL, ACM/IEEE Design Automation Conference, pp. 587-593, Jun. 1990.*
S. Kapoor et al., An Automatic Test Bench Generation System, 1994 VHDL International Users Forum, pp. 8-17, May 1994.*
Corno, et al., “Automatic Test Bench Generation for Validation of RT-Level Descriptions” IEEE Design Automation and Test Conference, Paris, Mar. 2000.

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