Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-09-03
2004-03-23
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S626000, C438S629000
Reexamination Certificate
active
06709970
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device having copper elements, and more particularly to a method for creating damascene interconnects using dual-step electroplating and annealing process.
2. Description of the Related Art
In integrated semiconductor devices, the speed and performance characteristics of a gate are influenced by gate thickness and length. As the size of the gates are reduced in higher-density integrated circuits, a higher resistance results from a corresponding reduction in conductor size and, when coupled with an associated capacitance of a dielectric inter-layer, can create significant signal propagation delays. To overcome such performance degradations, conventional aluminum conductors are being replaced with copper, which has a lower resistance than aluminum producing a resultant increase in gate speed.
The conductivity of copper is approximately twice that of aluminum and over three times that of tungsten. As a result, a same current can be carried through a copper line having half the width of an aluminum line, allowing for space-saving circuitry design. Also due to higher conductivity, copper consumes less power and, in addition, is less expensive than aluminum. Further, copper is approximately ten times less susceptible to degradation and breakage than aluminum and has superior electro-migration characteristics over those of aluminum. Thus, a copper line having a much smaller cross-section is better able to maintain electrical integrity than an aluminum line.
Disadvantageously, however, copper materially resists etching action of most conventional gaseous enchants, and thereby prevents fabrication of copper lines and copper plugs using conventional methods. Hence, a damascene process, and more particularly a two-step (dual-damascene) process, is usually employed. Such a process typically uses either a sputtering, electroplating, or CVD technique for metal-film deposition in the formation of copper lines and copper plugs.
Such techniques, however, involve complicated and expensive processing, since significant amounts of energy must be applied to a cupric metal compound to liberate or separate the copper from the metal compound for deposition on a surface where a semiconductor device is to be formed. Further, in a conventional sputtering process, deposition coverage may be inadequate due to the formation of voids. To overcome such problems, an electroplating process has been favored for the deposition of the copper layer.
A conventional manufacturing process for forming damascene copper interconnects in a semiconductor device will be described with reference to FIG.
1
. An insulating film
2
is deposited on a silicon substrate
1
, and then a via hole
5
is formed. A barrier-metal film
3
, e.g., consisting of TiN at a thickness of 20 nm, is deposited by sputtering on the entire surface. A seed-metal film
4
for growing copper plating consisting of copper is then deposited via sputtering (FIG.
1
(
a
)). Atypical sputtering environment may comprise, for example, a substrate temperature of 0 degrees C., a sputter power of 2 KW, a pressure of 2 mTorr, and a distance between a target and the substrate of 60 mm.
The substrate is then electroplated by immersing it in an aqueous solution of cupric sulfate at ambient temperature. The electroplated substrate is removed from the solution and “self-annealed” for 50 to 80 hours at ambient temperature to stabilize the structure of copper plating film
7
as shown in FIG.
1
(
b
). Following annealing, the substrate surface is polished by a chemical mechanical polishing (CMP) process to form damascene copper interconnects.
Disadvantageously, the aforementioned conventional manufacturing process has significant problems that can render a resultant semiconductor device unreliable. First, voids
6
may be generated inside a via hole or a groove due to the shrinkage of the thin copper plating during annealing as shown in FIG.
1
(
b
). This prevents full contact area with the substrate of subsequent depositions. Second, small grains in a seed-metal film deposited when forming the electroplated layer remain after the self-annealing, and lead to a less reliable device. Finally, the lengthy time for the annealing step yields extremely low throughput for the manufacturing process.
SUMMARY OF THE INVENTION
According to a preferred embodiment according to the present invention, a first method of creating damascene interconnects in a semiconductor integrated device having narrow and deep openings and wide and shallow openings on a same substrate comprises depositing a plurality of layers on a semiconductor substrate to create an assembly having a top layer; forming a narrow and deep opening and a wide and shallow opening through at least two of the plurality of layers of the assembly; depositing a protective barrier film on exposed surfaces of the assembly; depositing a seed metal film on the protective barrier film; depositing a first metal film, such that the narrow and deep opening is completely filled; annealing the assembly having the first metal film; depositing a second metal film on the first metal film such that the wide and shallow opening is completely filled; and immediately thereafter planarizing the assembly to the top layer of the assembly.
The first and second metal films may be selected from the group consisting of copper film, gold film, and platinum film. The assembly is preferably annealed at a temperature between about 150 to about 300 degrees C. for a period of time between about 3 minutes to about 30 minutes. The first and the second metal film may be deposited using an electroplating process or an electroless plating process. The seed metal film may be deposited using a CVD process or a sputtering process. The top layer of the assembly may be planarized using a CMP process.
According to another embodiment of the present invention, there is provided a second method for creating damascene interconnects having narrow and deep openings and wide and shallow openings in a semiconductor integrated device according to the present invention, comprising depositing a plurality of layers on a semiconductor substrate to create an assembly having a top layer; forming a narrow and deep opening and a wide and shallow opening through at least two of the plurality of layers of the assembly; depositing a protective barrier film on exposed surfaces of the assembly; depositing a seed metal film on the protective barrier film; depositing a first metal film; such that the narrow and deep opening is completely filled; annealing the assembly having the first metal film; cleaning any metal oxide on the first metal film; depositing a second metal film on the first metal film, such that the wide and shallow opening is completely filled; and immediately thereafter, planarizing the assembly to the top layer of the assembly.
The cleaning of the metal oxide on the first metal film may be carried out by a reduction process using hydrogen-based plasma or by a chemical etching process, wherein the chemical may be selected from the group consisting of inorganic acids and organic acids, such as H, H
2
SO
4
and HCl. The first and second metal films may be selected from the group consisting of copper film, gold film, and platinum film. The assembly is preferably annealed at a temperature between about 150 to about 300 degrees Centigrade for a period of time between about 3 minutes to about 30 minutes. The first and second metal film may be deposited using an electroplating process or an electroless plating process. The seed metal film may be deposited using a CVD process or a sputtering process. The top layer of the assembly may be planarized using a CMP process.
According to another embodiment of the present invention, there is provided a third method of creating damascene interconnects having narrow and deep openings and wide and shallow openings in a semiconductor integrated device, comprising depositing a plurality of layers on a semicon
Chung Ju-hyuck
Hah Sang-rok
Park Byung-lyul
Park Chankeun
Son Hong-seong
Lee & Sterba, P.C.
Quach T. N.
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