Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-02-24
2003-03-04
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S778000
Reexamination Certificate
active
06530058
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for correction of errors in a binary word stored in multilevel memory cells, not requiring additional cells.
BACKGROUND OF THE INVENTION
In order to detect and correct errors in a binary word with m bits, which is indicated hereinafter as the source word, techniques are known which are based on the addition of “redundancy” to the source word itself, i.e., which are based on the association of a binary word with k bits, which is indicated hereinafter as the correction word, with the source word, in which the k bits are obtained by carrying out k parity checks on k suitably selected sub-groups of the m bits in the source word.
This association is carried out in the so-called coding process, in which the 2
m
possible source words which can be defined by means of m bits, are mapped in a set of an equivalent number of binary words of m+k bits, which are indicated hereinafter as the code words, each of which is obtained by placing one after the other a source word and the corresponding correction word.
The value of each of the k correction bits assigned during the coding process depends on the type of parity check carried out. For example, the values of the k correction bits can be assigned according to the so-called even parity checking criterion, i.e., to the bit in the i-th position in the correction word is assigned the logic value 0 or 1 according to whether in the i-th sub-group of the source word there is respectively an even or odd number of logic values 1, or the values can be assigned according to the so-called odd parity checking criterion, i.e., to the bit in the i-th position in the correction word is assigned the logic value 0 or 1 according to whether in the i-th sub-group there is respectively an odd or even number of logic values 1.
The decoding process, in which, on the base of a code word containing m+k bits stored, there is determination of the corresponding source word with m bits, with detection and correction of any errors which have been generated in it during the storage period, is carried out by executing once again the k parity checks on the bits in the source word, and comparing the correction word thus obtained with the correction word which is read by the memory, in order to generate a check word, which is also of the binary type, and indicates the position of the error(s) present in the source word, and on the base of which the error(s) present in the source word stored can be corrected.
Implementation of the correction techniques of the above-described type thus involves not only storage of the source words, but also storage of the correction words which are associated with them, and thus the use of additional memory cells.
This inevitably gives rise to an increase in the dimensions of the memory matrix, compared with those which are strictly necessary for storing only the source words, and thus to an undesirable increase in the space occupied by the memory matrix itself, on the wafer on which it is produced.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides a method for correction of errors in a binary word stored in multilevel memory cells, not requiring the use of additional memory cells.
The method corrects the errors in a multilevel memory, by increasing the number of levels of the memory cells, instead of adding further memory cells. In other words, the method is based on the principle of storing, in each multilevel memory cell, instead of a whole number b of bits in the binary word to be stored, data units which are correlated to this binary word, and are expressed in a numerical base other than binary, and not a power of two. This is carried out by converting the binary word with m bits to be stored, from the binary base, to a base n, which is not a power of two, and by associating with the converted word a correction word, which is also formed from digits with a base n; the digits of the converted and correction words are then each stored in a respective multilevel memory cell, with a number of levels which is equivalent to the numerical base used for the conversion. This makes it possible to reduce the number of multilevel memory cells used, and for specific values of m and n, the saving is such that the detection and correction of errors does not require multilevel memory cells in addition to the m/b multilevel memory cells which would be necessary for storing the m bits in the binary word.
REFERENCES:
patent: 5122688 (1992-06-01), Grimes
patent: 5394362 (1995-02-01), Banks
patent: 5521865 (1996-05-01), Ohuchi et al.
patent: 5621682 (1997-04-01), Tanzawa et al.
Baker Stephen M.
Iannucci Robert
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
LandOfFree
Method for correction of errors in a binary word stored in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for correction of errors in a binary word stored in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for correction of errors in a binary word stored in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3048035