Method for correcting layout errors

Details Method for correcting layout errors Method for correcting layout errors

2007-12-18

2007-12-18

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

11191167

ABSTRACT:
A method for correcting layout errors of a layout, for example layout errors of a layout of an electronic circuit, is disclosed. In order to be able to correct such layout errors with the least possible complexity, the layout is examined for the presence of layout errors with the aid of predetermined design rules, identical layout errors are combined in a respective error class, and all layout errors of an error class that are still present are automatically corrected without further checking in an identical manner as soon as the correction of a layout error of the respective error class that is used as an error representative has been performed.

REFERENCES:
patent: 6063132 (2000-05-01), DeCamp et al.
patent: 6397373 (2002-05-01), Tseng et al.
patent: 2004/0025098 (2004-02-01), Meyer
patent: 102 24 417 (2003-12-01), None

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