Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-03-14
2006-03-14
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07013447
ABSTRACT:
A method for creating a vertical double-gate transistor design includes providing a planar transistor layout (10) having a gate layer (12) overlying an active layer (14). In one embodiment, a first intermediate layer (18) is defined based on an overlapping region of the gate and active layers, and, using the first intermediate layer, a second intermediate layer (22) is defined which defines a spacing between at least two fins of the vertical double-gate transistor design. The second intermediate layer may also define a length and a width of the at least two fins. One embodiment modifies a dimension of the first intermediate layer prior to defining the second intermediate layer. The method further includes defining a resulting layer (24) based on a non-overlapping region of the second intermediate layer and the active layer. The resulting layer may then be used to create a mask and a semiconductor device (30) corresponding to the vertical double-gate transistor design.
REFERENCES:
patent: 6189136 (2001-02-01), Bothra
patent: 6691297 (2004-02-01), Misaka et al.
patent: 6807662 (2004-10-01), Toublan et al.
patent: 2004/0117748 (2004-06-01), Tester
patent: 2004/0266115 (2004-12-01), Chan et al.
patent: 2005/0001216 (2005-01-01), Adkisson et al.
patent: 2005/0020020 (2005-01-01), Collaert et al.
Geppert, “Momentum Builds for Multiple-Gate Transistors,” IEEE, Spectrum, pp. 1-3 (2003).
Ohr, “FinFETs and InP Ics Vie for Dominance in Future Ics,” Silicon Strategies, pp. 1-4 (2003).
Nowak et al., “A Functional FinFET-DGCMOS SRAM Cell,” IEEE, 4 pgs., (2002).
Copy of related U.S. Appl. No. 10/074,732.
Mathew Leo
Min Byoung W.
Chiu Joanna G.
Freescale Semiconductor Inc.
Hill Daniel D.
Siek Vuthe
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