Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-12-17
2001-09-04
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S719000
Reexamination Certificate
active
06284665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a process for control of the shape of the etch front in polysilicon etching applications. The present invention also pertains to a method for recess etchback of a polysilicon-filled trench formed in a substrate, as well as a method for forming a polysilicon-filled trench capacitor in a single-crystal silicon substrate, the trench capacitor including a dielectric collar and a buried strap.
2. Brief Description of the Background Art
There are a number of methods described in the art for etching polysilicon films and for the etchback of polysilicon. Several of these methods are described below.
U.S. Pat. Nos. 4,895,810 and 5,182,234, issued Jan. 23, 1990 and Jan. 26, 1993, respectively, to Meyer and Hollinger et al., disclose depositing a dopant-opaque layer of polysilicon on a gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of a device, to provide control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structure formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile-tailored using a novel O
2
—SF
6
plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess conductive material. The sidewall spacers can be sized, either alone or in combination with profile-tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.
U.S. Pat. No. 5,229,315, issued Jul. 20, 1993 to Jun et al., discloses a method for forming an isolated film on a semiconductor device comprising the steps of: forming a deep and narrow cylindrical groove in a substrate; filling up the groove with an oxide film, and oxidizing a polysilicon layer encircled by the groove, thereby forming an isolated film in the shape of a cylinder. The method preferably includes the following steps: forming a pad oxide film and a nitride film on the substrate in that order; forming a mask window using a photoetching process, for depositing a polysilicon layer and for implanting field ions in the polysilicon layer; forming an insulated layer over the mask region for leveling the surface and then etching back the insulated layer to level the surface; etching the polysilicon layer and the substrate using a self-alignment method to form a deep cylindrical groove within the substrate; forming a CVD oxide film into the groove and over the polysilicon layer and etching it back by using a dry etching method to expose the polysilicon layer; and oxidizing the polysilicon layer to remove the nitride film.
U.S. Pat. No. 5,318,665, issued Jun. 7, 1994 to Oikawa, discloses the use of a mixed gas of HBr and Ar (10 to 25%) or a mixed gas of HBr, Ar (5 to 25%) and O
2
(0.2 to 2%) in etching a polysilicon film having a large step difference by means of the reactive ion etch (RIE) method.
U.S. Pat. No. 5,656,535, issued Aug. 12, 1997 to Ho et al, discloses a simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench, the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material. The disclosure of this patent is hereby incorporated by reference herein in its entirety.
European Patent Publication Nos. 0272143 and 0565212, published Jun. 22, 1988 and Oct. 13, 1993, and assigned to the assignee of the present invention, disclose a process for etching single crystal silicon, polysilicon, silicide and polycide using iodinate or brominate gas chemistry. The iodinate/brominate gas chemistry etches narrow deep trenches with very high aspect ratios and good profile control and without black silicon formation or other undesirable phenomena. The disclosure of these patent publications are hereby incorporated by reference herein in their entireties.
European Patent Publication No. 0814500, published Dec. 29, 1997, and assigned to the assignee of the present invention, discloses a method for etching metal silicide layers and polysilicon layers on a substrate with high etching selectivity and anisotropic etching properties. In the method, the substrate is placed in a plasma zone and process gas comprising chlorine, oxygen and, optionally, helium gas is introduced into the plasma zone. A plasma is formed from the process gas to etch the metal silicide layer at high etching selectivity relative to etching of the polysilicon layer, while providing substantially anisotropic etching of the metal silicide and polysilicon layers. Preferably, the plasma is formed using combined inductive and capacitive plasma sources. The disclosure of this patent publication is hereby incorporated by reference herein in its entirety.
European Pat. Publication No. 0821409, published January 28, 1998, by Coronel et al., discloses a collar etch method from DRAM cell. In the manufacture of 16 Mbits DRAM chips, a polysilicon strap is used to provide an electrical contact between the drain region of the active NFET device and one electrode of the storage capacitor for each memory cell. In a conventional fabrication process, a Si
3
N
4
pad layer is deposited onto the bare silicon substrate, then patterned. Next, deep trenches are formed in the substrate by dry etching. A classic ONO layer is conformally deposited into the trenches. The trenches are filled with undoped polysilicon. About 2.5 &mgr;m of undoped polysilicon is removed from the trench in a plasma etcher. A TEOS SiO
2
collar layer is conformally deposited, then anisotropically dry etched to leave only the so-called collar. Because trenches are present at the substrate surface, the thickness of the TEOS SiO
2
collar is not uniform. The above-referenced patent publication proposes a novel, highly selective dry etch method to anisotropically etch the TEOS SiO
2
collar while preserving the Si
3
N
4
pad layer thickness uniformity. A chemistry having a high TEOS SiO
2
/Si
3
N
4
selectivity (i.e., which etches TEOS SiO
2
faster than Si
3
N
4
by a factor of at least six) is used to etch the TEOS SiO
2
collar layer. C
4
F
8
/Ar and C
4
F
8
/Ar/CO mixtures which have respective selectivities approximately equal to 9:1 and 15:1 (depending on gas ratios) are adequate in all respects. When the surface of the Si
3
N
4
pad layer is reached (this can be accurately detected), the etch is continued by an overetch of the TEOS SiO
2
layer to ensure a complete removal of the horizontal portions thereof. The disclosure of this patent publication is hereby incorporated by reference herein in its entirety.
European Pat. Publication No. 0822593, published Feb. 4, 1998, by Haue et al., discloses a method of forming field effect transistors (FETs) on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer
Grimbergen Michael
Lill Thorsten
Applied Materials Inc.
Champagne Donald L.
Church Shirley L.
Utech Benjamin L.
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