Method for controlling lattice defects at junction and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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C438S154000, C438S301000

Reexamination Certificate

active

07320907

ABSTRACT:
A method for controlling lattice defects at a junction is described, which is used in accompany with an ion implantation step for forming a junction in a substrate and a subsequent annealing step. In the method, an extra implantation step is performed to increase the stress in the substrate apart from the junction, such that enhanced recrystallization is induced in the annealing step to lower the stress at the junction. The extra implantation step can be performed before or after the ion implantation step for forming the junction. A method for forming LDD or S/D regions of a CMOS device is also described, wherein at least one extra implantation step as mentioned above is performed before, between or after the ion implantation steps for forming the LDD or S/D regions of NMOS and PMOS transistors.

REFERENCES:
patent: 6294448 (2001-09-01), Chang et al.
patent: 6365472 (2002-04-01), Ishimaru et al.
patent: 6548361 (2003-04-01), En et al.
patent: 6680250 (2004-01-01), Paton et al.
patent: 6982433 (2006-01-01), Hoffman et al.

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