Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-05-09
2002-07-16
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
Reexamination Certificate
active
06421287
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit manufacture and, more particularly, to an apparatus and method for identifying and preventing improper shipment of integrated circuits from the circuit manufacturer to a customer or user.
2. Description of the Related Art
An integrated circuit is often referred to as a die or chip. Those terms are henceforth interchangeably used. A die may contain several thousand active and passive devices formed on a monolithic substrate. Those devices can be interconnected to form an overall circuit. Active devices include transistors, whereas passive devices include resistors and capacitors, for example.
Active and passive devices are formed and interconnected across the substrate using numerous fabrication steps, materials and equipment. To achieve precise placement of features which form an integrated circuit, a carefully carried out sequence of processing steps (e.g., deposition, etch, lithography, implant and/or heat cycles must be followed). Any deviation from the pre-set fabrication “recipe” will modify characteristics of the resulting product. In addition, any changes whatsoever to equipment used to implement the various steps will also modify the resulting product. For example, an ion implant concentration and/or energy from a specific ion implanter may be desired over other concentrations, energies or implanters. For this reason, many fabrication processes require specific types of equipment used to perform the various processing steps.
In addition to tracking the sequence and equipment used during the fabrication sequence, there may also be a desire to promote a particular arrangement of features which form the various active and passive devices. In this instance, the features are produced according to what is often called a “layout”. There may be numerous layout arrangements used for a specific integrated circuit depending upon the number of revisions that must be undertaken to achieve optimal performance, or performance which is more suitable to a specific application. As the layout changes, the various masks which form the integrated circuit also change. Typically, the revision number on each mask is imprinted on the resulting integrated circuit. The imprint is usually placed in a non-functional region of the integrated circuit and can be visually detected. Unfortunately, once the integrated circuit is removed from the wafer and encapsulated in a package, the revision number of the layout can no longer be discerned.
It would be desirable to track not only the particular processing recipe but also the layout revision, both of which are generically referred to henceforth as the manufacturing or “hardware” revision. It is intended that hardware revision encompass one or more, or a grouping of select parameters (e.g., processing steps, processing equipment, processing materials and/or layouts, etc.) used in forming active and passive devices on an integrated circuit. The tracking mechanism must be one which can detect a hardware revision attributable to an integrated circuit after the integrated circuit is removed from the wafer, placed in a package and possibly shipped to a customer. The mechanism of tracking hardware revisions after the integrated circuit leaves the manufacturing site proves beneficial, for example, in determining why or how the integrated circuit failed in the field.
Hardware revisions (i.e., revision to the processing recipe, processing equipment, or layout) used to produce a dissimilar version of integrated circuit product, are generally needed in order to perform changes to the final hardware product or possibly to experiment with changes to the product. Experimental results may help identify possible future enhancements to the hardware product
Experimental wafer lot runs are often referred to as non-qualification lots used by product engineers to ascertain, for example, possible causes of yield loss. By performing experiments on one or more wafers or one or more wafer lots, the product engineer can gather information useful in improving the integrated circuit performance or yield. Periodic experiments prove useful but only if packaged integrated circuits formed from those experiments are not inadvertently shipped to a customer. While a non-qualification wafer lot may pass final tests procedures, it may nonetheless be prudent not to ship integrated circuits derived from that lot. For example, if the experimental wafers demonstrate reliability problems, then the shipped integrated circuits may, over time, fail. It is not until the non-qualified wafers are qualified is it desirable to release that product to a customer. For this reason, it would be beneficial to not only track each and every hardware revision used to produce all the various parameters which involve integrated circuit manufacture, but also to prevent shipping non-qualified hardware revisions to a customer.
In addition to tracking hardware revisions, it may also be desirable to track software revisions. For example, many integrated circuits employ one or more memory elements arranged across the die. A popular memory device is one which can be electrically programmed after the die is manufactured, or possibly shipped to the customer. Once the storage elements are programmed, they are preferably non-volatile. Present non-volatile storage elements include, for example, programmable read only memory (“PROM”), fuses and/or anti-fuses, etc. Examples of popular PROMs include EPROMs, EEPROMs, or flash memory. The memory elements upon the die may be programmed either by the manufacturer or in the field. It may be important to keep track of the particular version of software used to program the memory elements since compatibility of that program version to a particular hardware revision used in forming the integrated circuit is important.
If an integrated circuit involves non-volatile memory elements then, in many instances, a customer will program the memory elements in the field using a software program revision which may or may not be compatible with the hardware revision shipped from the manufacturer. If the integrated circuit fails in its intended purpose, the customer or manufacturer will generally not know if the problem rests with the hardware or the manner in which the non-volatile storage elements were programmed. Typically, however, a manufacturer will know that a particular hardware revision is compatible with specific software revisions which, in most instances, are supplied directly or indirectly to the customer from the manufacturer. Thus, if a new hardware revision is released to the customer, then changes may be needed to the software program to form a new software revision compatible with that hardware. It is for this reason that it would be desirable to know if the hardware revision matches the software revision. More importantly, it would be desirable to read both the hardware and software revisions either at the customer or manufacturer site, possibly during program of the non-volatile memory. If, for example, the hardware and software revisions do not match, the customer can return the product to the manufacturer and receive updated hardware or software. The benefit of knowing a particular hardware revision and whether that revision is qualified for release to a customer would therefore prove an important benefit to the manufacturer along with knowing the particular software revision used in programming the integrated circuit at the customer site.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an electrically programmable integrated circuit, die or chip. Formed on a portion of the integrated circuit is a non-volatile storage location containing one or more storage elements. Certain storage elements may be programmed solely by the manufacturer preferably while the integrated circuit remains a part of a semiconductor wafer. A unique set of product engineering (“PF”) bits are programmed by the manufacturer into those storage elements within an address spa
Conley & Rose & Tayon P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
Nguyen Tan T.
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