Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Polycrystalline semiconductor
Reexamination Certificate
2000-05-24
2003-01-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Polycrystalline semiconductor
C438S478000, C438S301000, C257S412000
Reexamination Certificate
active
06511898
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor device manufacturing, and, more particularly, to a method and apparatus for controlling deposition parameters based on feedback of information relating to polysilicon grain size feedback.
2. Description of the Related Art
In the manufacture of semiconductor devices, wafers, such as silicon wafers, are subjected to a number of processing steps. The processing steps include depositing or forming layers, patterning the layers, and removing portions of the layers to define features on the wafer. One such process used to form the layers is known as chemical vapor deposition (CVD), wherein reactive gases are introduced into a vessel, e.g., a CVD tool, containing the semiconductor wafers. The reactive gases facilitate a chemical reaction that causes a layer to form on the wafers.
One exemplary deposition process involves the formation of polycrystalline silicon (polysilicon) layers on the wafer by reacting nitrogen (N
2
) and silane (SiH
4
) in a furnace. There are many factors that affect the deposition rate of a deposition tool. These factors include, among other things, the flow rate of reactive gases through the chamber and the temperature of the chamber. Typically, to determine the deposition rate for a particular tool (e.g., when it is first placed in service or after a maintenance event), a series of qualification wafers are processed and the resultant thickness of the process layer is measured. The measurements are used to estimate the deposition rate of the tool. Deposition times for subsequently processed wafers are determined based on the anticipated deposition rate.
Controlling the deposition process as described above helps achieve thickness uniformity, but not necessarily performance uniformity. Typically, a dopant material (e.g., boron, arsenic, phosphorous) is added to the polysilicon layers to lower the resistivity of the resulting layer. Correspondingly, the components of the finished semiconductor devices made from this layer (e.g., a gate electrode) also exhibit this lower resistivity. Generally, a device with a lower resistivity has a potential for a higher speed rating. A primary factor in determining the amount of dopant that can be introduced into the polysilicon is the grain size of the polysilicon. A structure with a smaller grain size has an increased number of grain boundaries, hence more sites for dopant ions to attach and a lower resistivity.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a processing line including a deposition tool, a metrology tool and a controller. The deposition tool is adapted to form a polysilicon layer on a wafer in accordance with a recipe. The metrology tool is adapted to measure a grain size of the polysilicon layer. The controller is adapted to modify the recipe for subsequently formed polysilicon layers based on the measured grain size.
Another aspect of the present invention is seen in a method for controlling a deposition process. The method includes forming a polysilicon layer on a wafer in accordance with a recipe; measuring a grain size of the polysilicon layer; and changing the recipe for subsequently formed polysilicon layers based on the measured grain size.
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PCT International Search Report for PCT/US01/12358, May 14, 2002.
Lansford Jeremy
Sonderman Thomas
Toprac Anthony J.
Advanced Micro Devices , Inc.
Le D
Nelms David
Williams Morgan & Amerson P.C.
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