Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reexamination Certificate
2000-08-23
2004-04-13
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
C710S100000, C710S104000, C710S107000, C710S109000, C710S305000, C710S009000, C710S052000, C359S199200, C370S391000
Reexamination Certificate
active
06721831
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital interface, and more particularly to a method for controlling a serial bus in a digital interface.
2. Description of the Related Art
In the latter 1980's, a rapid development of technology in digital audio/video device has increased the need for a high speed digital interface in home consumer electronic devices. As a result, the Institute of Electrical and Electronics Engineers (IEEE) 1394 serial bus has been gaining much interest. Physical connections among devices on the IEEE 1394 serial bus is by a cable which allows bidirectional data transmission. Also, each device has one or more cable connection ports for hot plugging to the IEEE serial bus, thereby enabling addition of a new node to or removal of a node from the bus.
Referring to
FIG. 1
, assume that an IEEE 1394 serial bus topology includes a digital TV
1
connected to a personal computer (PC)
2
, a DVCR
3
, a digital camcorder
4
, and a DVCR
5
; a CDROM
6
and a HDD
7
connected to the PC
2
and a HDD
8
connected to HDD
7
; a DVD RAM
9
connected to the DVCR
3
; and a PC
10
connected to the digital camcorder
4
, and a printer
11
and DVD RAM
12
connected to the PC
10
. A. bus reset is generated when a digital camera
13
is newly added to the IEEE 1394 serial bus. Due to a bus reset, a channel (CH) and bandwidth (BW) must be re-assigned to the previously connected devices such as the DVCR
5
, DVD RAM
9
, CDROM
6
and HDD
8
within a given time period of for example 1000 ms.
The bus configuration is automatically executed during the initialization of the bus and each of the devices, having several cable ports, acts as a repeater to form one local bus. Each port of each device on the bus also has logic for terminators, transceivers, arbitration, packet formatting, and data transfer control. Moreover, the IEEE 1394 serial bus transmits data for control and command using asynchronous packet data structure, and transmits real time data using isochronous packet data structure.
As a result, the IEEE 1394 serial bus has an Isochronous resource manager which provides three registers including a bandwidth available register (BAR), a channel available register (CAR), and a bus manager ID register (BMR) . The BAR is a register of 32 bits and indicates the size of the BW used in the isochronous communication.
FIG. 2
a
shows an example of a BAR. A node which needs to start an isochronous communication subtracts a bandwidth from a value of this register for use in the transmission and adds the bandwidth back after the transmission has been completed.
The CAR, as shown in
FIG. 2
b,
is a register of 64 bits and indicates the assigned state of CH used in the isochronous communication. Generally, a bit value of “0” indicates that a CH is being used while a bit value of “1” indicates that the CH is free, i.e. not being used. A node which needs to start an isochronous communication first confirms that the bit value corresponding to a CH for use in the transmission is “1” and converts the bit to a value of “0” before starting the transmission.
The BMR is a register of 32 bits and is used in deciding the bus manager, in which an initial value of 3Fh indicates that a bus manager does not exist. Thus, a node that wants to become the bus manager executes the bus manager's functions by first confirming that the register value is 3Fh and then by establishing its own node ID, within the given time period after a bus reset.
Furthermore, to convert the values of these registers, a compare swap lock transaction is used. Therefore, isochronous packet data is transmitted after establishing a CH and BW through the BAR and CAR.
Accordingly, if a bus reset is generated on the IEEE 1394 serial bus due to an addition or removal of a node while isochronous data is being transmitted to other nodes already connected, the nodes which have been transmitting isochronous data before the bus reset must receive reassignment of a CH and BW within the given time period following the self identifying process in order to continue the isochronous data transmission after the bus reset. Thereafter, a CH and BW, if available, is assigned to node(s) which needs to newly transmit isochronous data. However, in the bus control method in the related art, when a bus reset occurs due to an addition of a node, a CH and BW may not get reassigned to one or more nodes which have been transmitting isochronous data prior to the bus reset within the given time period. In such case, a CH may not be available and/or BW may not be sufficient because of other node(s) which needs to newly transmit isochronous data.
Therefore, although nodes that have been transmitting isochronous data prior to a bus reset have priority over nodes which needs to transmit isochronous data after a bus reset, a node which has been transmitting isochronous data prior to a bus reset may have to wait until a CH and BW becomes available to continue transmission of isochronous data,, if a CH and BW does not get reassigned during the given time period.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to solve at least the problems and disadvantages of the related art.
An object of the present invention is to provide a method for a more efficient control of a serial bus in a digital interface.
Another object of the present invention is to provide a method for controlling a bus in a digital interface which allows nodes on a serial bus to continue transmission of isochronous data that was being transmitting prior to a bus reset caused by new additions of one or more nodes.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein, a method for controlling a serial bus in a digital interface comprises determining whether a node requesting a CH and BW after a given period of time following a self identifying process due to a bus reset is one of either a new node or a previous node which had been transmitting isochronous data before said bus reset; determining whether at least one previous node has not been re-assigned a CH and BW before said given period of time, based upon a CSR, if said node is a new node; assigning a CH and BW to said node, and recording a Node ID and the assigned BW in positions of a RRR corresponding to the assigned CH of said node prior to starting an isochronous data communication, if at least one previous node has not been re-assigned a CH and BW before said given period of time; assigning a CH and BW to said node and starting an isochronous data communication, if there is no previous node which has not been re-assigned a CH and BW after said given period of time; re-assigning a CH and BW to said node after said given period of time by releasing a CH and BW assigned to a new node based upon the RRR, and starting an isochronous data communication, if said node is a previous node and if either one or both a CH and BW are not available; and re-assigning a CH and BW to said node after said given period of time and starting an isochronous data communication if said node is a previous node and if a CH and BW are both available.
REFERENCES:
patent: 5535208 (1996-07-01), Kawakami et al.
patent: 5815678 (1998-09-01), Hoffman et al.
patent: 5845152 (1998-12-01), Anderson et al.
patent: 5991520 (1999-11-01), Smyers et al.
patent: 6038625 (2000-03-01), Ogino et al.
patent: 6108718 (2000-08-01), Fujimori et al.
patent: 6509988 (2003-01-01), Saito
IEEE-SA Standards Board, IEEE Standard for a High Performance Serial Bus, 1995, IEEE Computer Society, pp 39-53, 211-242.*
Michael Johas Teener, IEE
Birch & Stewart Kolasch & Birch, LLP
King Justin
LG Electronics Inc.
Ray Gopal C.
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