Method for controlling a memory access

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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Details

C711S104000, C710S017000

Reexamination Certificate

active

07747832

ABSTRACT:
The invention relates to a method and a corresponding device for controlling a memory access, wherein a number of waiting states is established for the memory access to a storage device (FLASH/ROM, RAM, IO module) for a central control unit (CPU). A memory access is made possible in that the number of waiting states for the memory access is established individually as a function of an analysis of an instantaneous state (status) of the central control unit (CPU) and/or a type and/or address of the storage device (FLASH/ROM, RAM, IO module) being accessed.

REFERENCES:
patent: 5151986 (1992-09-01), Langan et al.
patent: 5155812 (1992-10-01), Ehlig et al.
patent: 5502835 (1996-03-01), Le et al.
patent: 5649161 (1997-07-01), Andrade et al.
patent: 5696917 (1997-12-01), Mills et al.
patent: 5813041 (1998-09-01), McIntyre et al.
patent: 6079001 (2000-06-01), Le et al.
patent: 6173392 (2001-01-01), Shinozaki
patent: 2002/0019898 (2002-02-01), Hayashi et al.
patent: 2002/0032829 (2002-03-01), Dalrymple
patent: 2002/0188820 (2002-12-01), Taruki
patent: 2005/0160246 (2005-07-01), Franke
patent: 01195552 (1988-01-01), None
patent: 02311943 (1989-05-01), None
patent: 06250914 (1993-02-01), None
patent: 06301641 (1993-04-01), None
patent: 07049780 (1993-08-01), None
patent: 07248960 (1994-03-01), None
patent: 10283255 (1997-04-01), None
patent: 2003044354 (2001-07-01), None
J. Handy, ‘The Cache Memory Book’, Copyright 1998, Academin Press, Inc. Second Edition, p. 204.
ARM7TDMI-S Technical Reference Manual, revision r4p3, ARM Limited, Mar. 11, 2004.
ARM7TDMI-S (Rev 3) Technical Reference Manual, ARM Limited, Sep. 2000.
Internet Archive Wayback Machine, retreived from internet Apr. 28, 2009 [url: http://web.archive.org/web/*/http://www.arm.com/sitearchitek/armwww.ns4/html/documentation?OpenDocument], pp. 1-5.
Internet Archive Wayback Machine, source code for Dec. 6, 2000 version of webpage http://www.arm.com/sitearchitek/armwww.ns4/html/documentation?OpenDocument, retreived from internet May 4, 2009, [url: http://web.archive.org/web/20001206122400/http://www.arm.com/sitearchitek/armwww.ns4/html/documentation?OpenDocument], pp. 1-35.
ARM, The ARM6 Family Bus Interface, Document No. ARM DAI 0018B, Dec. 1994, pp. 13-15.

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