Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-10-26
2002-07-23
Kim, Hong (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S154000, C713S002000, C365S049130
Reexamination Certificate
active
06425056
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to circuitry and protocols associated with operating cache memory in a computer system, and more particularly, to methods for controlling variously configured cache memory in a computer system.
BACKGROUND OF THE INVENTION
As processor speeds have rapidly increased in today's computer systems, the speed of economical memory devices has increased at a much slower pace. Thus, to take full advantage of the improved performance of today's faster and more powerful processors, faster and more expensive memory devices must be used. In order to reduce costs, however, most computer systems include a main memory populated by relatively economical (and slow) memory devices and a smaller cache memory populated by relatively expensive (and fast) memory devices. Commonly, the economical memory devices used in the main memory include dynamic random access memory devices (DRAMs), and the more expensive memory devices used in the cache include static random access memory devices (SRAMs). During computer system operation, the cache memory stores a subset of the data stored in the main memory. When a processor requests access to data stored in the main memory, that data may be more quickly provided if a copy is resident in the cache memory.
Referring to
FIG. 1
, a prior art cache memory subsystem
200
is depicted. The cache memory subsystem
200
includes a cache data array
202
that stores a subset of data stored in a computer system's main memory. A cache tag array
204
stores tag data associated with main memory addresses of the data currently copied in the cache data array
202
. A cache controller
206
is coupled with the cache data array
202
and the cache tag array
204
to monitor and control operation thereof.
When a processor wishes to read data from main memory, it drives an address on an address bus
208
, which is coupled with the cache memory subsystem
200
. A lower portion of the address bits carried on the address bus
208
indicate which of the various lines in the cache data array
202
may include a copy of the requested data. The lower portion of the address is applied to the cache tag array
204
, which responsively produces a corresponding tag value stored in the cache tag array. This tag value corresponds with the upper address bits of the data copied in the cache data array
202
. The cache controller
206
includes comparison circuitry (not shown) that compares the tag data output by the cache tag array
204
with an upper portion of the address bits carried on the address bus
208
. In the event the tag data and the upper portion of the address bits match (known as a “cache hit”), the cache controller
206
applies a plurality of control signals controlling access to the requested data copied in the cache data array
202
. The requested data is then provided to the processor via a data bus
210
coupling the processor with the cache memory subsystem
200
.
As is known to those skilled in the art, a wide variety of cache system configurations or organizations are commonly available for inclusion in computer systems. For example, a “direct-mapped” cache system is organized such that for each addressed location in main memory, there exists one and only one location in the cache data array that could include a copy of such data. In a “two-way set-associative” cache system, the cache is configured such that for any one addressed location in main memory, there exists two possible locations within the cache data array that might include a copy of such data. Typically, cache controller circuitry that monitors and controls a direct-mapped cache configuration is quite different from cache controller circuitry that monitors and controls a two-way set-associative cache configuration.
For the purposes of computer system performance and cost trade off studies, it is important that more than one cache configuration design be available for testing in a given computer system. Ideally, reconfiguration of the cache memory system would be straightforward and inexpensive to reduce testing time and expense. In today's computer systems, different cache memory configurations require different cache controller hardware. This requires two or more separate system design revisions to be developed in order to test multiple cache memory configurations in a given computer system. This leads to longer design cycles and, if more than one cache configuration is to be included in manufactured products, additional inventory must be maintained. In the case of today's computer systems including the Intel Pentium-type processors, different L
2
cache configurations require different motherboard designs with significantly different components. Computer systems having readily reconfigurable cache memory subsystems are not currently available.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for controlling a cache memory in a computer system. The method includes determining in which of first and second cache configurations the cache memory is organized. A memory address is received, and corresponding tag data stored in the cache memory is then retrieved. If the cache memory is of the first configuration, then first tag data are retrieved and compared to the memory address. If the cache memory is of the second cache configuration, then second tag data are retrieved and compared to the memory address.
The first and second cache configurations may be direct-mapped and two-way set-associative configurations, respectively. Determining cache configuration may include receiving a configuration signal and determining which of first and second states the signal has. The first and second tag data may be compared to different first and second portions of the memory address, respectively. If the cache memory is of the second configuration, the first tag data may be retrieved and compared to the second portion of the memory address.
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82430FX PCIset Datasheet 82437FX System Controller (TSC) and 82438FX Data Path Unit (TDP), Intel Corp, pp 14 & 45, Nov., 1996.
Dorsey & Whitney LLP
Kim Hong
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