Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-01-05
2001-04-17
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S107000
Reexamination Certificate
active
06219735
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to information processing systems such as personal computers and workstations. More particularly, it relates to techniques for controlling the bus of an information processing system.
2. Description of the Related Art
In an information processing system, a plurality of modules connected to a bus for the transfer of data in synchronism with a common clock. A technique for controlling the synchronous bus is known from, for example, the official gazette of Japanese Patent Application Laid-open No. 11872/1986.
Such a prior-art control of the synchronous bus will be explained.
FIG. 16
of the accompanying drawings illustrates the timings of data transfer on the bus according to the synchronous bus controlling technique in the prior art.
Referring to the figure, symbol CLK denotes a synchronous clock for data transfer, which is common to all modules connected to a bus. Symbol A/D denotes an address and data which are multiplexed together. An address valid signal ADRV indicates that the address of the signal A/D is valid. A signal WRITE serves to designate a write access, and it also indicates that the data of the signal A/D is valid. In addition, a wait signal WAIT serves to notify a master side of the fact that a buffer on a slave side is not in a status capable of accepting the data.
In a case where one of the modules is to access another for a write operation by the use of the bus configured of such signal lines, the bus master first asserts the address valid signal ADRV indicating the validity of the address on the line A/D, and it simultaneously delivers the address of the access destination to the line A/D.
On the other hand, the slave module senses that the write access is directed toward itself, on the basis of the decoded result of the address and the designation signal WRITE for the write access. In a case where the slave module is ready for accepting the data, it accepts the valid data on the line A/D at the timing of the synchronous clock CLK. In contrast, in a case where the slave module is not ready for accepting the data, it requests the prolongation of a data cycle by the use of the wait signal WAIT which notifies the master side that it is incapable of accepting the data.
In a case where the wait signal WAIT is asserted, the master module prolongs the data cycle during the assertion. When the slave module is ready to accept the data, it accepts the valid data on the line A/D at the timing of the synchronous clock CLK, and it negates the wait signal WAIT. Upon the negation of the wait signal WAIT, the master module finishes the data cycle and ends the access.
In this manner, according to the prior-art technique for controlling the synchronous bus, the master module transfers the data to the slave module, and during the report to each other whether or not the data transfer is possible, using the wait signal WAIT in a handshake fashion.
SUMMARY OF THE INVENTION
With the prior-art technique as stated above, in transferring the data, a wait cycle is inserted in advance of the data transfer. Therefore, an overhead arises in correspondence with the wait cycle, to incur problems that the data transfer rate is lowered and that the utilization factor of the bus is lowered due to an increased bus occupation time period.
It is accordingly an object of the present invention to provide a bus control method in which the utilization factor of a bus can be enhanced by reducing the overhead of data transfer.
In order to accomplish the object, the present invention proposes by way of example, a bus control method in an information processing system having a bus, and a plurality of modules connected to the bus, wherein a master which is the module having acquired mastership of the bus controls the bus and transfers an address and data to a slave which is the module being a transfer destination, in synchronism with cycles of a clock which is common to all the modules; comprising the step of allowing a specified one of the modules to acquire the bus mastership and so become master module; the step of allowing the master, having acquired the bus mastership, to execute a transfer cycle for transferring either of the address or the data to the slave, and to thereafter release the bus mastership; the step of allowing the module having received either of the transferred address and data as slave, to send all the other modules an acknowledge report indicating receipt of either of the address or the data, a predetermined number of cycles after the transfer cycle in which either the address or the data is transferred; and the step of allowing the module which executed the transfer as the master the predetermined number of cycles before the cycle in which the acknowledge report is sent, to verify success of the transfer in accordance with the sent acknowledge report.
According to the bus control method of the present invention, when the master has acquired the mastership of the bus, it executes the transfer cycle for transferring the address and the data to the slave, without checking the status of the slave, and it releases the bus mastership without verifying the success or failure of the transfer. On the other hand, the module having received the transferred address and data as the slave sends all the other modules the acknowledge report indicative of the receipt for each transfer cycle concerning the received address or data, the predetermined number of cycles after the corresponding transfer cycle. The module having executed the transfer as the master the predetermined number of cycles before the cycle in which the acknowledge report has been sent, verifies the success or failure of the transfer in the executed transfer cycle in accordance with the sent acknowledge report. Only when the transfer is not successful, is a countermeasure taken.
Accordingly, the transfer to the slave which is ready to accept this transfer from the master can be realized by only the cycle in which the address or data is actually transferred. Thus, the utilization factor of the bus can be enhanced.
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Gemma Hideaki
Kaneko Seiji
Komori Kazuhiko
Kondo Nobukazu
Okada Tetsuhiko
Antonelli Terry Stout & Kraus LLP
Auve Glenn A.
Hitachi , Ltd.
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